[moved] How to get the internal timestep in verilog-a and hspice?

[yhzhang0916]

Hello, I am doing a simulation using a verilog-a model in hspice. I want to know how to get the internal timestep that hspice/verilog-a was using during the transient simulation. Since I found the internal timestep is always changing in each iteration, can I get a log file to show the internal timestep in each iteration?

Thank you in advance

 

[sleepless_nights]

Hi @yhzhang0916 ,

I'm not sure how to get the timestep, but you can bound it in your Verilog-A code using the system function $bound_step. It limits the timestep to be no longer than its argument.

For more information, you can refers to Ken Kundert's book The Designer's Guide to Verilog AMS. I hope it helps.

Kind regards,
Vitor