pumperthruster
Newbie level 4
I am designing a new circuit that samples an input signal from 1Mhz to 6Mhz(0-1 volt sinusiod). I will use a fast 12bit ADC to capture this signal at 20Mhz. The ADC has a parallel output. I am deciding whether to use either an FPGA or CPLD to grab one single data chunk from the ADC(its a one shot device), lets say the first 8K samples, then do an FFT or even simpler calculation on the stored data. Depending on the result of this calculation, the devise should output a 1 or a 0. That's it. Price is critical. This whole process gets repeated every minute or so.
So. question.
1) Do FPGA's or CPLD's have embedded sram. (this would save me adding a separate sram chip). I'd need at least 8Kx8 (64Kb)minimum. That gives me 8000 byte samples (less for 12bit of coarse)
2) What's the cheapest device out there to do the job, any recommendations?
3) for this application, do I go for CPLD or FPGA? (Note, cost is critical, and ease of design too, I'm no wizard when it comes to programming these devices - in fact I have yet to learn)
Ferd.
So. question.
1) Do FPGA's or CPLD's have embedded sram. (this would save me adding a separate sram chip). I'd need at least 8Kx8 (64Kb)minimum. That gives me 8000 byte samples (less for 12bit of coarse)
2) What's the cheapest device out there to do the job, any recommendations?
3) for this application, do I go for CPLD or FPGA? (Note, cost is critical, and ease of design too, I'm no wizard when it comes to programming these devices - in fact I have yet to learn)
Ferd.