Brittoo
Member level 5
Hello all
Here are some of my doubts:
1.Why does carrier mobility reduce with temperature for pmos/nmos?
2.Why do low Vt devices have high leakage?
3.Why does the voltage drop happen when the nmos is used to generate a logic "high"?
4. Why do series connected "n" number of nmos/ pmos have a threshold drop of just Vdd -Vth and not Vdd -n(Vth)?
Regards
Brittoo
Here are some of my doubts:
1.Why does carrier mobility reduce with temperature for pmos/nmos?
2.Why do low Vt devices have high leakage?
3.Why does the voltage drop happen when the nmos is used to generate a logic "high"?
4. Why do series connected "n" number of nmos/ pmos have a threshold drop of just Vdd -Vth and not Vdd -n(Vth)?
Regards
Brittoo