Moore code understanding

[ek4m2005]

hello every one,
i want to know and understand the code of the moore fsm for at leas 2 states.
regardes
mohamed

 

[D.A.(Tony)Stewart]

Moore is combinational,

primitive example
Let C= {Not A & Not B} OR {A & B}
we say here C = Exclusive OR of {A,B} = XOR{A,B}

https://en.wikipedia.org/wiki/XOR_gate

 

[BlackHelicopter]

Moore is combinational,

primitive example
Let C= {Not A & Not B} OR {A & B}
we say here C = Exclusive NOR of {A,B}

I have no idea what you're talking about. That makes zero sense.

 

[ek4m2005]

thnx 4 ur reply, but i need to understand the finite state machines (FSM) that built in vhdl can be written by moore code, how ? i want to under stand it
regardes

 

[D.A.(Tony)Stewart]

WHen you use combinational logic that may include memory or stored states, we call this the Moore (combination logic) machine.

This is the Sequential Logic term. https://en.wikipedia.org/wiki/Moore_machine ( read my XOR example and this link.

The more generally used name is now called the Finite State Mchine. for more detail

https://en.wikipedia.org/wiki/Finite-state_machine
or FSM

Now you can begin VHDL implementations.

 

[ek4m2005]

i think this is a simple code for one or two states but i don't understand it, where the state and the transitions and the conditions and the input and the output and why he use (type)??
if u know a simple code for FSM moore code plz help
regrdes

---

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-- This is a sample state-machine using enumerated types.
-- This will allow the synthesis tool to select the appropriate
-- encoding style and will make the code more readable.
 
--Insert the following in the architecture before the begin keyword
   --Use descriptive names for the states, like st1_reset, st2_search
   type state_type is (st1_<name_state>, st2_<name_state>, ...); 
   signal state, next_state : state_type; 
   --Declare internal signals for all outputs of the state-machine
   signal <output>_i : std_logic;  -- example output signal
   --other outputs
 
--Insert the following in the architecture after the begin keyword
   SYNC_PROC: process (<clock>)
   begin
      if (<clock>'event and <clock> = '1') then
         if (<reset> = '1') then
            state <= st1_<name_state>;
            <output> <= '0';
         else
            state <= next_state;
            <output> <= <output>_i;
         -- assign other outputs to internal signals
         end if;        
      end if;
   end process;
 
   --MOORE State-Machine - Outputs based on state only
   OUTPUT_DECODE: process (state)
   begin
      --insert statements to decode internal output signals
      --below is simple example
      if state = st3_<name> then
         <output>_i <= '1';
      else
         <output>_i <= '0';
      end if;
   end process;
 
   NEXT_STATE_DECODE: process (state, <input1>, <input2>, ...)
   begin
      --declare default state for next_state to avoid latches
      next_state <= state;  --default is to stay in current state
      --insert statements to decode next_state
      --below is a simple example
      case (state) is
         when st1_<name> =>
            if <input_1> = '1' then
               next_state <= st2_<name>;
            end if;
         when st2_<name> =>
            if <input_2> = '1' then
               next_state <= st3_<name>;
            end if;
         when st3_<name> =>
            next_state <= st1_<name>;
         when others =>
            next_state <= st1_<name>;
      end case;      
   end process;

---

 

[TrickyDicky]

thats the template for a state machine. The state transitions are in the NEXT_STATE_DECODE process, and the registering of the state is in SYNC_PROC

 

[ek4m2005]

i want to know why he put (type) function

 

[rberek]

A type is used to provide names for the states which makes the code more readable.

r.b.

 

[TrickyDicky]

the synthesisor will chose the encoding for the states when it synthesises the code. You can usually specify the type of coding you want (standed count, one hot, grey code etc) with the default being one hot for 3 or more states (at least for altera).

 

[ek4m2005]

thnx, but if i made for ex. 40 state, should i write them in type?

 

[rberek]

That's entirely up to you!

r.b.