shaiko
Advanced Member level 5
Below is a VHDL code for an asynchronous state machine :
When I try to simulate the above with modelsim I get the following error:
What should I do in order to make the code simulatable ?
Code:
asynchronous_fsm : process
(
reset ,
address ,
data ,
general_register_1 ,
general_register_2 ,
event_register ,
mask_register ,
events ,
dsp_on ,
state ,
any_event_detected ,
unmasked_event_detected
) is
begin
if reset = '0' then
dsp_on <= '0' ;
general_register <= ( others => '0' ) ;
mask_register <= ( others => '0' ) ;
event_register <= ( others => '0' ) ;
fsm_state <= fsm_idle_state_0 ;
else
case state is
when idle_state =>
if any_event_detected = '1' then
event_register <= events ;
if unmasked_event_detected = '1' then
state <= on_state ;
dsp_on <= '1' ;
end if ;
end if ;
when on_state =>
if general_register_1 ( 0 ) = '0' then
dsp_on <= '0' ;
state <= idle_state ;
end if ;
if address = mask_register then
mask_register <= data ;
elsif address = general_register_1_address then
general_register_1 <= data ;
elsif address = general_register_2_address then
general_register_2 <= data ;
end if ;
end case ;
end if ;
end process asynchronous_fsm ;
When I try to simulate the above with modelsim I get the following error:
Error: Iteration limit reached at time 1 ns.
What should I do in order to make the code simulatable ?