mahmood.n
Member level 5
It is stated in a book (VHDL for logic synthesis) that
How that is done?! The standard negation is to invert all bits and add 1 to that. Otherwise, doing (0 - 3) to achieve -3 means that the zero has to borrow a number from higher order digit and that is not possible. Isn't that?
Assume we want to calculate -3. That means
Another question.
In the patterson's book (computer architecture: hardware/software interface) and for dividing signed numbers, it is stated that
Now if you use google to calculate (-1) mod 4, you will get +3 that means (this link)
-1 = -1 * 4 + 3
which contradicts patterson's statement. I also see similar thing in the VHDL book (attachment)
Any idea?
Code:
5.6.3 Minus Sign
The minus sign is implemented as a 2’s-complement negation. 2’s-complement negation is performed by subtracting the input from zero.
How that is done?! The standard negation is to invert all bits and add 1 to that. Otherwise, doing (0 - 3) to achieve -3 means that the zero has to borrow a number from higher order digit and that is not possible. Isn't that?
Assume we want to calculate -3. That means
Code:
000
-011
------
Another question.
In the patterson's book (computer architecture: hardware/software interface) and for dividing signed numbers, it is stated that
Code:
This anomalous behavior is avoided by following the rule that the dividend and
remainder must have the same signs, no matter what the signs of the divisor and quotient.
We calculate the other combinations by following the same rule:
+7 / –2: Quotient = –3, Remainder = +1
Now if you use google to calculate (-1) mod 4, you will get +3 that means (this link)
-1 = -1 * 4 + 3
which contradicts patterson's statement. I also see similar thing in the VHDL book (attachment)
Any idea?
Attachments
Last edited: