minimize drain or source capacitance?

[inquisitive]

Given an option that you can minimize either drain or source capacitance, which capacitance would you minimize and why?

 

[gingerjiang]

in my understand, when there are even fingers in multifinger MOS, the number of drain isn't equal to that of source based on the layout selection, so the parasitic capacitance between drain or source and substrate is different

 

[ieropsaltic]

Well, that depends on the application .For digital circuits ,for example, it is usually required to reduce the drain capacitance because the drain node is usually connected to output while the source is usually connected to GND or Vdd .Thus, by decreasing the drain capacitance, less delay ad power consumption can be achieved .

For analog applications, I believe you should check the node where the pole is required to be reduced and reduce its capacitance .It may also include a compromise and optimization as you may encounter Miller multiplication for example .