Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Hhow to minimize or eliminate EMI effect in the IC Layout or Circuit Design?

Status
Not open for further replies.

mpig09

Full Member level 4
Joined
Aug 26, 2005
Messages
232
Helped
8
Reputation
16
Reaction score
2
Trophy points
1,298
Location
Taipei
Activity points
2,810
Hi all:

My IC is easy to malfunction due to EMI interference.
I did two experiments to verify it:
based on the same PCB Board and the experiment environment,
I compare my chip and competitor's, the result shows my chip
easy to effect by EMI.

The malfunction :
  1. some Register values are error
  2. Outputs Interrupt for no reason

My chip communication interface is I2C.

If you have any relevant paper or doc, please sharing to me.
If you have any suggestion, please let me know.


Thanks.

mpig
 

Many ways to fail; start by learning to provoke the problem(s)
repeatably and at will. Then you can determine causes and
solutions.

Collecting a basket of conjectures only brings anecdotes, not
understanding. And you'd like to understand, so as not to
repeat.
 
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top