voho
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MIG, DDR2 and Virtex5
Hi,
can someone who has used Xilinx's MIG DDR2 controller help?
i am trying to generate and simulate the DDR2 controller with memory
MT47H16M16 memory model generated by MIG 2.0 (Xilinx ISE 10.1
> SP3)
If someone has a tutorial or ise example.
thanks in advance
Hi,
can someone who has used Xilinx's MIG DDR2 controller help?
i am trying to generate and simulate the DDR2 controller with memory
MT47H16M16 memory model generated by MIG 2.0 (Xilinx ISE 10.1
> SP3)
If someone has a tutorial or ise example.
thanks in advance