cocopa
Junior Member level 2
Hello, I'm using Microsemi Libero Soc v11.8 to develop VHDL code for an IGLOO nano FPGA.
The problem I have, is that for a certain net the tool automatically adds an input clock buffer and I am not allowed to allocate the net to the pin I want, only to global clock pins.
How can I disable this? In Xilinx there was a constraint "clock_dedicated_route = false", is there something similar in microsemi's tool?
Thank you.
The problem I have, is that for a certain net the tool automatically adds an input clock buffer and I am not allowed to allocate the net to the pin I want, only to global clock pins.
How can I disable this? In Xilinx there was a constraint "clock_dedicated_route = false", is there something similar in microsemi's tool?
Thank you.
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