Sunayana Chakradhar
Member level 5
Hello All,
I am trying to synthesize and implement a soft microblaze core to know the approximate resource utilization on my Zynq FPGA. I am following the document and video from xilinx mentioned in the link below.
https://www.youtube.com/watch?v=VjYdNIOyRcE
https://www.xilinx.com/support/docu...3_1/ug940-vivado-tutorial-embedded-design.pdf
https://www.xilinx.com/support/docu..._notes/xapp1093-amp-bare-metal-microblaze.pdf
What I dont understand is why have they taken a AXI UART and AXI GPIO IP core in this design. Are these same as the AXI UART that connect to Zynq PS?
Are these used to connect to external UART modules or do they behave like a internal AXI bus to connect microblaze to Zynq. Please clarify.
I am trying to synthesize and implement a soft microblaze core to know the approximate resource utilization on my Zynq FPGA. I am following the document and video from xilinx mentioned in the link below.
https://www.youtube.com/watch?v=VjYdNIOyRcE
https://www.xilinx.com/support/docu...3_1/ug940-vivado-tutorial-embedded-design.pdf
https://www.xilinx.com/support/docu..._notes/xapp1093-amp-bare-metal-microblaze.pdf
What I dont understand is why have they taken a AXI UART and AXI GPIO IP core in this design. Are these same as the AXI UART that connect to Zynq PS?
Are these used to connect to external UART modules or do they behave like a internal AXI bus to connect microblaze to Zynq. Please clarify.