Metal Width for VDD/VSS

[isaacnewton]

If the total current is 1 mA, what's the Metal Width (layout) for VDD or VSS? Thanks.

 

[sengyee88]

It depends on the metal current density, that will be stated in the design rule manual.
Width needed = Required Current/Current density at high temp
If area is not a concern, try to give a bit more allowance.

 

[mpkp123]

Yes u can calculate the width using the above procedure.
But, remember always give atleast 205 more than the minimum required.
and, for the power lines take as much as u can.

 

[muiyuen]

Yes, depending on what metal layer you use for the Vdd/Vss, the respective metal current density should be followed. The design manual would contain the information or formulas for you to calculate the minimum width, but if more space is available, then the metal layer could be made wider.

 

[piao]

When you use the wide metal, u also need to take into account the slot. and this rule is also shown inside the design rule from foundry.

 

[cad_slvr]

Is the question here process independent?

I was assuming for 90nm, 65nm and below, there would be higher restrictions as far as the width of the metal is concerned.

And wouldn't it also depend on where the metal is being used, is it for interconnect, input signaling or power rail?

 

[ersachinkalra]

The reason behind having a proper metal width for VDD/VSS power rails is that if you put metal l;ayer with width lesser than required then the effect of Electromigration comes into picture and this can cause Open circuits.
and if you put a metal width more than required then this can cause extra Parasitic capacitance which can degrade the performance of the circuit and also can lead to latch up.

for deciding metal width for VDD/VSS the length of the metal line,current desity should be taken into consideration.

The logic with length of metal wire is related to IR drop caused by the VDD/VSS rails. If you can measure the length of the metal rail for VDD/VSS then you can calculate No. of squares of metal..

In the Technoogy file there is a term ohm/square....i.e sheet resistance per square of the metal. with which you can calculate the total resistance of the wire and with I x R you can get the voltage drop on VDD/VSS..where I is the max current flowing through the power rails.

This voltage drop should be less than 10 mV for Analog circuits and 5 mV for digital circuits.

 

[sengyee88]

and if you put a metal width more than required then this can cause extra Parasitic capacitance which can degrade the performance of the circuit and also can lead to latch up.

Isn't it good if you have more parasitic cap at the supply line, that can act as supply filter? Assuming there are no active circuits sitting below the power line (I think this is a reasonable assumption).

Maybe you can explain more about how this parasitic cap induce latch up.

 

[hr_rezaee]

hi
in 0.18u you must use 1u.
regards

 

[Fom]

During ESD testing 4KV HBM the current pulse can reach up to 2 - 2.5A within 100-150nsec.
So for I/O it is better to layout power lines as wide as possible.

 

[YESH_23]

the metal width design iis according to the current carrying capability of the particular metal/micro meter.
caluculate according to it.
for this value refer to the design document

 

[renwl]

During ESD testing 4KV HBM the current pulse can reach up to 2 - 2.5A within 100-150nsec.
So for I/O it is better to layout power lines as wide as possible.

The average current is more important,isn't it?
:?:

 

[Yun Lin]

During ESD testing 4KV HBM the current pulse can reach up to 2 - 2.5A within 100-150nsec.
So for I/O it is better to layout power lines as wide as possible.

The average current is more important,isn't it?
:?:

Yes, normally, we only consider average current, not the peak current.

 

[mists]

not average, but rms value.