ITing
Newbie level 3
ddr2 burst
Hi,everyone
I want to write a ddr2 controller in VHDL.
Now, there is a problem in front of me.It is burst length.
In JEDEC standard its value is 4 or 8. when it's 4, it means if you write a data in location0 the location 1,2,3 in the same columne will be assert one by one.The data keep in the location 1,2,3 would be overwrite. How can i keep data safe? The length of data i will write is not fixed, but in byte.
thanks.
Hi,everyone
I want to write a ddr2 controller in VHDL.
Now, there is a problem in front of me.It is burst length.
In JEDEC standard its value is 4 or 8. when it's 4, it means if you write a data in location0 the location 1,2,3 in the same columne will be assert one by one.The data keep in the location 1,2,3 would be overwrite. How can i keep data safe? The length of data i will write is not fixed, but in byte.
thanks.