matlab in Design development

[shitansh]

Hi all,

Recently I put on one project from middle phase.

In this project some team members had developed matlab code to varify algoridhm and now I need to develop RTL from that algoridhm.

I never used matlab till now. and i think matlab is used to prove algoridhm only

Can any body tell me how matlab proves algoridhm?
Is rtl developmet becomes easy once matlab code written? if not then what is its perpose?

Also elobrate more for this kind of design methodology if possible.

Thanks
Shitansh Vaghela

 

[mbenton]

Hello,

In matlab you can manipulate data much easier, and you can see much faster if an algorithm would work or not.

Maybe I'm wrong but I dont think it becomes easier to write code once you have matlab code, because there could be more efficient ways of doing something than following the matlab code.
For example if you'd have in matlab

a=x/abs(x)

In vhdl you would only take the highest bit of x and the result would be the same

signal x : std_logic_vector(N downto 0);
....
a<=x(N)

I think that the whole point of using matlab before is to see if the concept works. To avoid writing whole RTL code and than see that the ideea was a bad one.

On a side note, matlab is capable of generating vhdl code from matlab code. I dont know how optimum the generated code is but it can be done. Look up: system generator.

 

[zape]

Matlab is a very useful tool for people desingning algorithms.

If you are at the next stage, so "translating" matlab to an FPGA design, you should start studying the algotithm itself, operations used, data size, fixed or floating point, if operations are simple or you need filters, FFTs, etc...
As mbenton recommends, Xilinx System Generator is a nice tool that integrated as one of Matlab-Simulink toolboxes easies design and verification. If you are not FPGA expert this is a good starting point

 

[shitansh]

Xilinx System Generator is a nice tool that integrated as one of Matlab-Simulink toolboxes easies design and verification. If you are not FPGA expert this is a good starting point

But I think if we generate hdl code using system generator then it will be a technology dependent rtl, what about if we want to generate technology independent rtl code from matlab algo?

 

[TrickyDicky]

Simulink has an HDL coder addon that produces techonology independent HDL. It allows you to co-simulate hand coded HDL too.

 

[shitansh]

Simulink has an HDL coder addon that produces techonology independent HDL. It allows you to co-simulate hand coded HDL too.

Hi,

Do you have any kind of tutorial or any doc in which process shows to generate verilog code from matlab code.

I need to generate verilog code from matlab code which is written by some other persom

Thanks
Shitansh Vaghela

 

[TrickyDicky]

Its not as simple as that. Only a subset of m code can be HDL coded, and then the M code has to be written in a hardware friendly way to ensure that it will produce meaningful hardware. Its not as simple as taking an algorithm and clicking "to FPGA".

you will basically have to reconstruct the algorithm using the existing code as the verification base. Luckily you can generate HDL from stateflow too, so control logic is alot easier to control.

 

[zape]

You should not forget also all the hardware resources you may need, internal or external memory, etc...

It has been some time since last time I used SysGen, but one limitation existed was that only one clock could be used.

Do not forget the HW, behing verilog or vhdl there is an FPGA which is HW.

 

[mpatel]

Try to make Simulink model from your algorithm and then replace it using System Generator blocks. It is better to have Simulink model in any case of dealing with hardware design.

If your algorithm is written in .m files then use Xilinx AccelDSP. I developed signal processing algorithms and also used Altera DSP Builder in Simulink. It makes the whole work lot easier. And yes, Altera DSP Builder and Xilinx System generator both support multi-clock design but timing violation can not be checked using these tools.

I hope it helps.
Mukesh

Addition: You can generate synthesizable HDL code from Simulink automatically which is technology independent. Consider that also.

 

[eltonjohn]

Hi Friends .
Matlab is a nice language that can hide the data dependency and the programming model .Which means that is mostly a SIMULATION language .It relies a lot on internal functions for which there is not source code equivalent .That richness of functions is what makes matlab so powerfull .To derive either sequential code or concurrent code for hardware .It requires a CONVERTER .This usually is called a synthesis program . Which is sold by somebody else .And those tools can be very expensive .I mean very ,very expensive .So matlab is a great tool to craft ALGORITHMS .Not to implement them .Well you had mention all kinds of bridges to synthesis already .But once i know that my algorithm works .I would take my time t to see what is required to port it to a plataform. Simulation to synthesis is the game .But there are so many factors to think that there is just a simple way .I have hundreds of embedded books with code examples to use .I have never used those examples .I always end up using my own code .For whatever reason .So there is no miracle solution .The engineer has to be professional to analyze what is required .And no to expect an automatic code translator.

If we want to continue analyzing the matlab language .Lets compare it to other simulation languages like VHDL or verilog ( yes this are simulation languages too!!).
What is the difference and why matlab is better ? .Well matlab is a script language to start .The other two require run time systems to operate . Matlab syntax i much ,much easier to deal with . There are almost no data types to declare ..Try that with VHDL !.. You just name it and use it .NO WASTE OF TIME in matlab . Of course you are also more prone to mistakes .You can add apples and oranges .But if you are using matlab you must be very intelligent so you will pay attention . (@#$%!!)
The drawback is that program execution is slower .But who cares when you need to verify algorithms . I mentionned VHDl and Verilog .But the same applies to C or C++, Fortran and Ada .Those languages have very heavy programming environments .But on the other side are very general . You use libraries for all the complex stuff . One library could calculate the relativistic time delay of a satellite when it get closer to the moon. In matlab the same was solved by using functions .Pre-compiled functions .Either internal or external .But those functions are not open source .Otherwise anybody could make "FULL MATLAB COMPATIBLE" tools .This is not possible .So that function has to be synthetized by a tool when porting matlab code to another plataform .
The code produced may not be very optimized ..Or cheap !

Well i love all this .Matlab ,Vhdl ,C generators simulators etc. But also i hate it too when it doesn't works !

 

[shitansh]

Thanks eltonjohn & all other members for explanation.

I found one way to make it possible. Since my algorithm was written in .m file I first tried to understand all syntex of that files and then try to understand logic used in algorithm.

Now next for synthesis if I use simulink then code will be library dependent and I wanted to have generic rtl code for that which can be used on any platform.

So next one by one I started to implement logic in verilog which was used in algorithm of matlab files. Yet I have not verified but hope it will work with condition I implemented correct functionality in rtl.

Thanks again all of you.