A
ahmadagha23
Guest
Dear friends,
When I map my "rst" signal (which is an input signal) to GCK0 pin in sp2e the mapper send an error message that it can not combine two symbols rst and rst_BUF to a single IOB GCK0. But after I using the (rising) edge of "rst" signal the mapper could assigne the "rst" to GCK0 pin would you know why?( I had not this problem in CPLDs.) If I do not need to use any edge of "rst" signal in my VHDL code What can I do for mappin "rst" to GCK0??
regards
When I map my "rst" signal (which is an input signal) to GCK0 pin in sp2e the mapper send an error message that it can not combine two symbols rst and rst_BUF to a single IOB GCK0. But after I using the (rising) edge of "rst" signal the mapper could assigne the "rst" to GCK0 pin would you know why?( I had not this problem in CPLDs.) If I do not need to use any edge of "rst" signal in my VHDL code What can I do for mappin "rst" to GCK0??
regards