Making A processor in Verilog

[habibparacha]

hi!
I am having trouble in making a pipelined processor in verilog. It is my semester project and I don't know form where to start.
Can someone kindly guide me and tell the steps and simple procedure to make this processor.

Thanks in advance.

 

[bassa]

search through the forum
https://www.edaboard.com/threads/102155/#post451867

you can find some lecture notes here

 

[jamesbowman]

This is an open-source RISC CPU with a 4-stage pipeline:

AEMB Embedded Core | AESTE