Mains zero cross circuit

[cupoftea]

Hi,

We need a zero cross circuit which gives a falling edge 430us +/-50us before the zero cross. The attached is the best we can come up with. Do you have better?

Its for 100VAC +/-15%

LTspice and jpeg attached

 

[KlausST]

Hi,

430us before rising, falling or both zero cross?

At 50Hz this means at 13.47% of the amplitude.
Now there are 3 problems:
1) is the input frequency stable enough?
2) is the input amplitude accurate and stable enough?
3) is the input waveform pure sine without overtones?

Klaus

 

[D.A.(Tony)Stewart]

Aren't there supposed to be two ZCS pulses per cycle?

50 Hz +/- ?

 

[wwfeldman]

what frequency?
you can detect a zero crossing, then wait ??? us so you can be 430us +/-50us before the next one
clearly the synchronization has to take place before you try doing whatever you want to do 430 us early

+/- 50 us is a large tolerance

50 Hz means a zero crossing every 10 ms - 10000us
wait 600 us after a zero crossing - should be 400 us before the next zero crossing

 

[KlausST]

Hi,

+/- 50 us is a large tolerance

Yes and no.
If it comes from a diesel generator, it's rater difficult, because frequency, voltage and distortion .. all cause timing errors.

If it comes from mains .. still not very easy. It depends on "dirty" loads are nearby.

It's 15.0% vs 13.5%.
So if the amplitude varies by 1.5% you get 50us variation. Not uncommon at mains voltage.

Klaus

 

[dick_freebird]

You have to say what constitutes "better". I'm guessing
dirt cheap is somewhere near the top of the list.

Back in the antedeluvian '80s working on high value
medical equipment, I liked a more complicated ZCD to
tag the crest (for firing SCR motor control, at or after)
which integrated the line voltage (off a handy input xfmr
tap) with an op amp and used a comparator on the lagged
output's zero crossing to get the peak. We did not care
about accuracy, to measure or know, but you could lash
it up and assess.

So that's halfway to next zero and you might get better
absolute tolerance from a one-shot if you make it last
half as long.

Integrating also stands to clean up incoming line trash....

The best accuracy in this scenario, I imagine, would be a
PLL whose counter happens to roll over a logically nice
number right where you want it. A matter of selecting the
reference frequency perhaps. A needier solution than
desired most likely, but the most noise-resilient in the
output timing I expect.

My money's still on "dirt" though.

 

[D.A.(Tony)Stewart]

Back in the pre-Cambrian days of the 70's, I did a weekend design and built for a 1kW color organ, so I made a cheap N dirty ZCD.

The AC voltage was current limited and scaled down then amplified by an AC coupled CMOS inverter, then an XOR gate with 1 path delayed 1 us to produce the ZCD pulse. The ZCD was also used to dump a negative sawtooth voltage and a variable Vref to a comparator controlled the phase to a pulse coil to Triac.

 

[cupoftea]

thanks, in the sim of the top post, we need the down going edge at "read" pin to be 430us before zero cross...whether 5hz or 60hz mains, and over 100vac +/-15%.
It is Japan mains.

 

[KlausST]

Hi,

no idea how to do it the analog way.

Thus I´d go the digital way.
Mains --> filter --> true zero cross comparator --> uC capture interrupt
--> calculate period time --> subtract 430us --> add to capture value --> set as new interrupt event

If you need a pin to toggle then use a waveform generation periferal.

Note: the mains filter will introduce some lag time. you may compensate this by modifying the "subtract 430us" value.

Klaus

 

[D.A.(Tony)Stewart]

Consider a tuneable precision one-shot where the trailing edge is phase-locked to the limited AC logic signal desired transition with null error. Make it anyway you want.

 

[KlausST]

Hi,

Consider a tuneable precision one-shot where the trailing edge is phase-locked to the limited AC logic signal

It's not clear to me how a phase locked circuit can generate a constant "pre-delay" while the frequency may change from 5 to 60Hz.
A PLL can generate constant phase .. but how constant time.

Klaus

 

[D.A.(Tony)Stewart]

Hi,


It's not clear to me how a phase locked circuit can generate a constant "pre-delay" while the frequency may change from 5 to 60Hz.
A PLL can generate constant phase .. but how constant time.

Klaus

In a Type II PLL, the inputs are edge-sensitive, meaning they are sensitive to either rising or falling edges of the input signals. Here are the key points

1. Edge Sensitivity: Type II PLLs can synchronize to the trailing edge of the input signal. This means that the PLL's output clock will align with the trailing edge of the input signal.
2. Locked Indicator: After the PLL is locked (Locked = 1), the leading edge of the output clock will always be a constant time delay before the trailing edge, ensuring that the output is synchronized to the zero-crossing point.
3. Phase+Frequency Locked Loops: Type II PLLs are suitable for both analog and digital applications, and they can lock not only the phase but also the frequency of the output signal to the input signal.
4. Phase Difference: Unlike Type I PLLs, which typically have a 90-degree phase difference between the input and output, Type II PLLs have a 0-degree phase difference. This means that the output is in phase with the input signal.
5. Sensitivity to Phase Noise: While Type II PLLs offer the advantage of a 0-degree phase difference, they are more sensitive to phase noise. This sensitivity to phase noise can be acceptable or even advantageous in some applications, but it might not be suitable in situations where phase noise is a critical concern.

--- Updated Oct 17, 2023 ---

This is a quick N dirty design using parts of the CD4046 PLL , 74HC123 monostable and a CD4007 Inverter. But using only one pulse per cycle. Adding an XOR gate will do both edges.

 

[KlausST]

Hi,

This does not answer my question on how to generate the constant 430us timing .. considering the 5..60Hz input frequency.

I surely understand how a PLL works.

Klaus

 

[BradtheRad]

The sinewave volt levels match at 430 uSec after a zero crossing and before.
Therefore sample-and-hold voltage 430 uSec into the positive polarity waveform.

Next time sinewave is at that exact voltage is 430 uS before positive waveform ends.
Works with any frequency. (Edit: highest limit is about 580 Hz.)

 

[D.A.(Tony)Stewart]

Hi,

This does not answer my question on how to generate the constant 430us timing .. considering the 5..60Hz input frequency.

I surely understand how a PLL works.

Klaus

Forgive me for not explaining.

I used the precision 1-shot IC circled in a diagram below.

Analog could be one-half of the dual 74HC123.

Digital could be an asynch binary counter with 1MHz XO and masked by gates for 423 us cycles. like a 74HC4060 with gates to reset after 423 us.

This was late 70's technology, that I once used and also in Falstad simulator.

A PIC uC could replace both 1 shot and PLL.

The front-end filter would need some TVS or MOV and maybe additional low Q BPF filtering, but I just showed a lead-lag attenuator with no phase shift going into a self-biased logic inverter to create the square wave.

I added an XOR frequency-doubler to get both zero-crossings simulated here

.

--- Updated Oct 18, 2023 ---

Oops the 1-shot delay must be on the synthesized output feedback, not the line clock

 

[dick_freebird]

Having designed one of those (on a now dead technology) I can
say there's no such thing as a precision one-shot of that style.
Sloppy comparator, even if you used 1% R and 5% C you are stuck
with the datasheet variability of timing which is not great. That's
where you start thinking about clocks, counters and complexity.

And wander far from (say it with me now)....

But for somebody doing digital power converter control this is
probably almost a freebie.

 

[D.A.(Tony)Stewart]

Having designed one of those (on a now dead technology) I can
say there's no such thing as a precision one-shot of that style.
Sloppy comparator, even if you used 1% R and 5% C you are stuck
with the datasheet variability of timing which is not great. That's
where you start thinking about clocks, counters and complexity.

And wander far from (say it with me now)....

But for somebody doing digital power converter control this is
probably almost a freebie.

When the required tolerance on delay is +/-20%, a trimmer adjustment with a stable supply can easily achieve this or even a few %.

 

[KlausST]

Forgive me for not explaining.

Thanks for your effort.

I feel too dumb to see how this can generate an edge 430us ahead of the true ZC signal.
In my eyes it gives a second edge after the ZC signal.

But anyways, it's not important that I understand it, it's more important that it works for the OP.

Klaus

 

[D.A.(Tony)Stewart]

No , I was the dumb one for putting the 1shot on the grid signal path, when it must be put on the feedback VCO path to mixer. (to advance the time)

https://tinyurl.com/ylyytjaa

I made the 1-shot big = 1 ms so it is easier to scope. This is just a value that is edited with the alternate mouse click on the symbol.

RESET starts the 50 cycle or so capture time.

 

[KlausST]

Hi,

Oh, now I undeestand. This makes sense.
For the "lock" you use the delayed signal, so you know the "not delayed" edge is 430us ahead. Clever.

...
The PLL needs to precisely lock on a 1:12 input frequency range. But this is a different challenge.

Klaus