Logical net having multiple drivers

[adivy]

Hello,

I'm using Lattice ECP2M device with diamond 2.2.
I'm facing with multiple drivers error when connecting the output of ILVDS buffer to the input of a DDR IP component.
HOw can I prevent this?

 

[TrickyDicky]

dont connect multiple drivers together?

 

[imbichie]

Can you post the exact error and the design part here, i have worked with lattice ECP2, with LVDS, i think these ILVDS and OLVDS buffers are too old, If you wants to use the LVDS, you can directly declare the pin type as LVDS, then the I/O buffers will insert automatically.

 

[adivy]

Hi Shibin,

Thanku for the reply.

THe piece of code I'm having problem with is following:

i_data_ddr: ddr_gen
port map
(
Del(3 downto 0) => (others=>'0'),
CLK => clk_out,
Rst => rst,
Data(6 downto 0) => data(6 downto 0),
Q(13 downto 0) => data_sdr );



gen:for i in 1 to 7 generate
data_in : ILVDS
port map
(
A => i_data_p(i-1),
AN => i_data_n(i-1),
Z => data(i-1)
);
end generate;

Error message displayed during translate is:
ERROR - ngdbuild: logical net 'data[0]' has multiple drivers
ERROR - ngdbuild: logical net 'data[1]' has multiple drivers
ERROR - ngdbuild: logical net 'data[2]' has multiple drivers
ERROR - ngdbuild: logical net 'data[3]' has multiple drivers
ERROR - ngdbuild: logical net 'data[4]' has multiple drivers
ERROR - ngdbuild: logical net 'data[5]' has multiple drivers
ERROR - ngdbuild: logical net 'data[6]' has multiple drivers
ERROR - ngdbuild: DRC failed with 7 errors and 0 warnings
Done: error code 2

- - - Updated - - -

I basically want to take in DDR LVDS data into the ECP2 device.

 

[imbichie]

From my understanding, here data(6 downto 0) is the LVDS port, and which is connected to your DDR Data(6 downto 0).
If your ports are LVDS, then no need of ILVDS or OLVDS buffers in the top rtl, you can treat the data(6 downto 0) as normal port, and you need to specify the data(6 downto 0) ports as LVDS25, LVDS33, etc in your *.lpf file and you can assign the LVDS positive pins to this ports.
So when the synthesis tool see the ports as LVDS in the *.lpf file, then the tool will assign the buffers automatically. Also it iwll assin the LVDS positive pins to the corresponding ports also assigns the LVDS negative pins to the corresponding LVDS negative ports.

Simply you need to assign the RTL design LVDS ports to the positive LVDS pins of the FPGA, then the tool will automatically assign the negative LVDS pins by inserting suitable LVDS buffer at the port side.

 

[TrickyDicky]

You dont show the components, so we cannot see if you're driving 2 outputs with the same signals.

 

[mrflibble]

i have worked with lattice ECP2, with LVDS, i think these ILVDS and OLVDS buffers are too old ...

In what way too old? That, and do you happen to know if ECP3 / MachXO2 share the same lvds issue you are referring to?

 

[imbichie]

In what way too old? That, and do you happen to know if ECP3 / MachXO2 share the same lvds issue you are referring to?

Hi mrfibble,

What i meant old is, now the isplever tool can insert the ILVDS and OLVDS buffers automatically if we are define the ports as LVDS in the *.lpf file, so no need of using those ILVDS and OLVDS primitives in the Top RTL.
We can treat the LVDS ports as Normal IO ports in the design and only we need to define the port type as LVDS25/LVDS33/LVDS25s, etc. and also need to assign the RTL port to the positive LVDS pin of the FPGA, so during the synthesis the tool will insert the corresponding ILVDS/OLVDS buffer and also assing the negative LVDS pin of the FPGA.

Also i think in the current ECP2 library these ILVDS and OLVDS primitives are not there.

Here the issue is with multiple driving of data(6 downto 0), it may be cause because of this assignment, If not , then we need the complete Design code to find the multiple driven issue.

- - - Updated - - -

For more details you can refer the reference design from lattice

http://www.latticesemi.com/en/Products/DesignSoftwareAndIP/IntellectualProperty/ReferenceDesigns/ReferenceDesigns01/71LVDSVideoInterface.aspx

go to the download path and download the source, extract the zip file and go to the project folder select the vhdl or verilog then have a look on the *.lpf of ECP2,
Also you can look the source rtl code *.v or *.vhd files for the top module design

 

[mrflibble]

Hi mrfibble,

What i meant old is, now the isplever tool can insert the ILVDS and OLVDS buffers automatically if we are define the ports as LVDS in the *.lpf file, so no need of using those ILVDS and OLVDS primitives in the Top RTL.
We can treat the LVDS ports as Normal IO ports in the design and only we need to define the port type as LVDS25/LVDS33/LVDS25s, etc. and also need to assign the RTL port to the positive LVDS pin of the FPGA, so during the synthesis the tool will insert the corresponding ILVDS/OLVDS buffer and also assing the negative LVDS pin of the FPGA.

Ah, thanks! I think I understand what you mean now. Older versions of synth tool did not automatically instantiate LVDS buffers. Newer versions has the option to do this automagically for you. Right?

And thanks for the LVDS video interface link. Filed away for future reference.