lithium
Member level 1
bus arbiter verilog
Hi all,
have a project which is described as follows:
Multiple units in a system can share a bus but only one unit can use it on any clock cycle. Unit that wants to use the bus make a request and then receive the “GRANT” signal at the start of the next clock cycle.
implement an arbiter for a bus with 8 units connected to it. The centralized parallel arbitration is usually used in many system busses and in high-speed I/O busses. In general, the bus transaction rate can be improved by overlapped arbitration scheme
(perform arbitration for next transaction during the current transaction) or bus parking (master can hold onto the bus and perform multiple transactions as long as no other device makes the request)
kindly help me any material for the above problem.
thanks in advance,
Lithium
Hi all,
have a project which is described as follows:
Multiple units in a system can share a bus but only one unit can use it on any clock cycle. Unit that wants to use the bus make a request and then receive the “GRANT” signal at the start of the next clock cycle.
implement an arbiter for a bus with 8 units connected to it. The centralized parallel arbitration is usually used in many system busses and in high-speed I/O busses. In general, the bus transaction rate can be improved by overlapped arbitration scheme
(perform arbitration for next transaction during the current transaction) or bus parking (master can hold onto the bus and perform multiple transactions as long as no other device makes the request)
kindly help me any material for the above problem.
thanks in advance,
Lithium
