LDO Design using Folded Cascode as Error Amp

[KKR]

Dear Members,
I am working on Low Power LDO design, Vin( 1.6-3.2V) and Vout (1.2V) and total current consumption except load current( 1uA-60mA) is 10 uA( Including Bias Ckt, BGR, etc). I have to use Folded cascode architecture as error amp and PMOS as Pass Transistor with resistor divider.
As I have very low current to operate the error amp, I have designed it in 4uA: 2uA in NMOS input stage(Input pair in subthreshold ) and 2uA for load transistor.My output voltage swing is 0.35-1.2V, which is input to PMOS pass transistor.The current through resistor divider is set to be 2 uA.I have calculated the PMOS pass transistor dimension ratio using full load 60 mA and Vdsat 200mV. It comes to be 30,000.
1) is it the right way to calculate the Pass Transistor dimension ratio?
2) By putting above dimension ratio for full load current, when I check the dc condition, all is well. i.e pass transistor is in saturation and rest of the transistor are in saturation.But when I do it for same, pass transistor is in cutoff and two transistor(M5 & M14) from error Amp goes to linear.
3) Right know I am concentrating only on dc biasing and haven't gone for compensation for stability.
4) Is this the right way? if yes or not please help me to come out of this so that i can move further. I am attaching the schematic in fig

 

[checkmate]

1) is it the right way to calculate the Pass Transistor dimension ratio?

Just simulate your pmos transistor with gate tied to gnd (or maybe a few mV), with max current load and min input voltage, across all corners, required sizing to achieve output of 1.2V.

2) By putting above dimension ratio for full load current, when I check the dc condition, all is well. i.e pass transistor is in saturation and rest of the transistor are in saturation.But when I do it for same, pass transistor is in cutoff and two transistor(M5 & M14) from error Amp goes to linear.

The biasing for V_bias2 and V_vias3 does not work. Just use a single diode connected MOS, and size accordingly. Also, for LDO, the worst case operation for the pass transistor is linear (ie full on), not saturation.

3) Right know I am concentrating only on dc biasing and haven't gone for compensation for stability.
4) Is this the right way? if yes or not please help me to come out of this so that i can move further. I am attaching the schematic in fig

You are doing fine. The compensation will not affect the DC biasing. Just fix the points stated above.