Layout question on signal path wires

[ee484]

Layout question

Hi, all.


I am currently doing layout for my chip.
As far as I know, I'd better place as many contacts as possible in the empty space in the chip so that they work as bypass capacitor.
Since I placed many contacts (for VSS and VDD), the signal wires have to run through these contacts. Of course, the signal path wires are MET2 and VSS and VDD underneath signal wires are MET1.

I am worrying anything below signal paths (in this case MET1 of VSS and VDD).

Please help me if you have any experience.

Another short question is if it is okay for a signal wire to run through VSS or VDD, then should I have to run a wire in parallel ? Or, it does not matter because VSS and VDD are DC.

Thank you all.

J

 

[Grig]

Re: Layout question

Hi
I think you need extract parasitic coplings of signal to suply path
add package parasitics to your schematic
simulate this one
and see
This is common approach to control layout influence to electrical performance

 

[Brittoo]

Re: Layout question

Hi, all.


I am currently doing layout for my chip.
As far as I know, I'd better place as many contacts as possible in the empty space in the chip so that they work as bypass capacitor.
Since I placed many contacts (for VSS and VDD), the signal wires have to run through these contacts. Of course, the signal path wires are MET2 and VSS and VDD underneath signal wires are MET1.

I am worrying anything below signal paths (in this case MET1 of VSS and VDD).

Please help me if you have any experience.

Another short question is if it is okay for a signal wire to run through VSS or VDD, then should I have to run a wire in parallel ? Or, it does not matter because VSS and VDD are DC.

Thank you all.

J

hi ee484

It is quite okay to route your M1 signals under M2 power rails , but make sure that critical and noisy signals in the circuit are shielded with power or gnd lines on both the sides.This is when you need to take care , coz running M2 pwr lines on M1 Gnd lines are not recommended as there is just one metal difference between the 2. Hope that helps.

Regards
Brittoo

 

[manish12]

Re: Layout question

this type is for redusing the crosstalk between signals for lon run wires.

 

[RyanLin]

Re: Layout question

Did you used mos capacitance? that can get more capacitance and used less area in your layout when decuping capacitance desn,t need accurate

 

[laglead]

Re: Layout question

It depends on the sensitivity of the signal line and the noise on the VDD/VSS line.

 

[leohart]

Re: Layout question

Hi, all.


I am currently doing layout for my chip.
As far as I know, I'd better place as many contacts as possible in the empty space in the chip so that they work as bypass capacitor.
Since I placed many contacts (for VSS and VDD), the signal wires have to run through these contacts. Of course, the signal path wires are MET2 and VSS and VDD underneath signal wires are MET1.

I am worrying anything below signal paths (in this case MET1 of VSS and VDD).

Please help me if you have any experience.

Another short question is if it is okay for a signal wire to run through VSS or VDD, then should I have to run a wire in parallel ? Or, it does not matter because VSS and VDD are DC.

Thank you all.

J

Hi,but how do u use "as many as possible contact in empty space as bypass cap"???how A contact can be bypass cap,will you elaborate that?
As I've noticed that you use m2 as signal wiring and m1 for power lines,is that common sense ?PLS tell me about that,THX

Added after 5 minutes:

Hi, all.


I am currently doing layout for my chip.
As far as I know, I'd better place as many contacts as possible in the empty space in the chip so that they work as bypass capacitor.
Since I placed many contacts (for VSS and VDD), the signal wires have to run through these contacts. Of course, the signal path wires are MET2 and VSS and VDD underneath signal wires are MET1.

I am worrying anything below signal paths (in this case MET1 of VSS and VDD).

Please help me if you have any experience.

Another short question is if it is okay for a signal wire to run through VSS or VDD, then should I have to run a wire in parallel ? Or, it does not matter because VSS and VDD are DC.

Thank you all.

J

hi ee484

It is quite okay to route your M1 signals under M2 power rails , but make sure that critical and noisy signals in the circuit are shielded with power or gnd lines on both the sides.This is when you need to take care , coz running M2 pwr lines on M1 Gnd lines are not recommended as there is just one metal difference between the 2. Hope that helps.

Regards
Brittoo

Hi
"Shielded with power or gnd lines on both sides" means left and right or up and down?If there are only two metals,it's hard to shield the signal line totally.
why m2 pwr lines on m1 gnd are not recommended?Risks for breakdown?
But I do see the book"IC mask essenitials"use this configuration for free decouple cap between vdd and gnd...

 

[Brittoo]

Re: Layout question

Hi leohart

Shielding can b e achieved in different ways. You can have 2 gnd lines or pwr lines running parallel along the the critical signall length.This can still b achieved with 2 metals.
Well, i do think that M2 pwr over M1 gnd increases the possibility of pwr rails getting shorted. Any comments regarding this would be helpful.

Regards
Brittoo