sanjaysharmaiitk
Member level 1
i am facing problem in post-layout simulation.
if you know about post-layout simulation on HSPICE tool.
please help me.
i have to modified "Johnson_count.pex.netlis" file adding VDD, VSS input-port..
main modules "Johnson_count" are not connected . there are no "vdd " & "gnd" port in in "Johnson_count.pex.netlis" after extraction.
how to connect supply vdd vss
note:
"VDD" and "VSS" rings are used for supply and ground respectively in layout.
..............................................................................................................................................................
Detail about design is given below.//
////////////////////////////////////
*Johnson counter verilog code have been used for design.
*post synthesis simulation has been completed.
*DRC ,LVS ,PEX has been completed.
Following cad tool are used :
1>layout => Innovus (Encounter)
DRC,LVS,PEX => calibre
(PEX in spice view)
three file are generated.
1>Johnson_count.pex.netlist
2>Johnson_count.pex.netlist.JOHNSON_COUNT.pxi
3>Johnson_count.pex.netlist.pex
*i used "tsl18fs120_scl_no_supply_pins.cdl"
for verilog format to cdl format conversion. { for LVS }
Testbench for counter is written in spice format and
simulated on HSPICE (synopsys tool).
no error and 2 warnings are coming.
////////////////////////////////////////////////////////////////////////////////////////////////
**warning** the following singular supplies were terminated to 1 meg resistor
supply node1 node2
(counter.sp:14)v1 0:vdd defined in subckt 0 0:0 defined in subckt 0
(counter.sp:15)v2 0:vss defined in subckt 0 0:0 defined in subckt 0
(/users/resstaff/sanjaysh/synopsys_designs_SCL/Hspice/counter/Johnson_count.pex.netlist:801)v1 1:vdd defined in subckt johnson_count 0:0 defined in subckt 0
(/users/resstaff/sanjaysh/synopsys_designs_SCL/Hspice/counter/Johnson_count.pex.netlist:802)v2 1:vss defined in subckt johnson_count 0:0 defined in subckt 0
Warning:'No DC path nodes' occurs 2201 times
No DC path from the following nodes,connected with gdcpath:
-------------------------------------------
|Node |Subckt |
|---------------------------+-------------|
|n1 |0 |
|n9 |0 |
|out[0] |0 |
|out[1] |0 |
|out[3] |0 |
|out[4] |0 |
|out[5] |0 |
|out[6] |0 |
|out[7] |0 |
|x1.n_vdd_xout_reg[1]/mm19_d|johnson_count|
-------------------------------------------
Warning:'1 connection nodes' occurs 1 times
Summary of 1 connection from the following nodes:
-----------------------
|Node |Subckt |
|----------+----------|
|out[2] |0 |
-----------------------
///////////////////////////////////////////////////////////////////////////////////////end
spice output are not matched with expected output .
if you know about post-layout simulation on HSPICE tool.
please help me.
i have to modified "Johnson_count.pex.netlis" file adding VDD, VSS input-port..
main modules "Johnson_count" are not connected . there are no "vdd " & "gnd" port in in "Johnson_count.pex.netlis" after extraction.
how to connect supply vdd vss
note:
"VDD" and "VSS" rings are used for supply and ground respectively in layout.
..............................................................................................................................................................
Detail about design is given below.//
////////////////////////////////////
*Johnson counter verilog code have been used for design.
*post synthesis simulation has been completed.
*DRC ,LVS ,PEX has been completed.
Following cad tool are used :
1>layout => Innovus (Encounter)
DRC,LVS,PEX => calibre
(PEX in spice view)
three file are generated.
1>Johnson_count.pex.netlist
2>Johnson_count.pex.netlist.JOHNSON_COUNT.pxi
3>Johnson_count.pex.netlist.pex
*i used "tsl18fs120_scl_no_supply_pins.cdl"
for verilog format to cdl format conversion. { for LVS }
Testbench for counter is written in spice format and
simulated on HSPICE (synopsys tool).
no error and 2 warnings are coming.
////////////////////////////////////////////////////////////////////////////////////////////////
**warning** the following singular supplies were terminated to 1 meg resistor
supply node1 node2
(counter.sp:14)v1 0:vdd defined in subckt 0 0:0 defined in subckt 0
(counter.sp:15)v2 0:vss defined in subckt 0 0:0 defined in subckt 0
(/users/resstaff/sanjaysh/synopsys_designs_SCL/Hspice/counter/Johnson_count.pex.netlist:801)v1 1:vdd defined in subckt johnson_count 0:0 defined in subckt 0
(/users/resstaff/sanjaysh/synopsys_designs_SCL/Hspice/counter/Johnson_count.pex.netlist:802)v2 1:vss defined in subckt johnson_count 0:0 defined in subckt 0
Warning:'No DC path nodes' occurs 2201 times
No DC path from the following nodes,connected with gdcpath:
-------------------------------------------
|Node |Subckt |
|---------------------------+-------------|
|n1 |0 |
|n9 |0 |
|out[0] |0 |
|out[1] |0 |
|out[3] |0 |
|out[4] |0 |
|out[5] |0 |
|out[6] |0 |
|out[7] |0 |
|x1.n_vdd_xout_reg[1]/mm19_d|johnson_count|
-------------------------------------------
Warning:'1 connection nodes' occurs 1 times
Summary of 1 connection from the following nodes:
-----------------------
|Node |Subckt |
|----------+----------|
|out[2] |0 |
-----------------------
///////////////////////////////////////////////////////////////////////////////////////end
spice output are not matched with expected output .