jitter formation and reduction

[balamanikandan]

hi,

How jitter is formed when we divide the clock or use multiphase interleaving?

How it can be avoided or minimized?

 

[goldsmith]

Dear balamanikandan
Hi
It is simple . jitter will create when you generate a high frequency square wave with a single stage . but if you create a higher one ( higher than your desired ) and then divide it to achieve your desired frequency , thus the jitter time , will divide too .
Best Wishes
Goldsmith