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AboutVerilog syntax: Verilog LRM
About synthesizable subset and coding for synthesis:
Verilog Compiler User Guide – from Synopsys Documentations
General about synthesis and STA (in Synopsys environment):
Synopsys Chip Synthesis Workshops and DC, PrimeTime User Guide, Reference Manuals – from Synopsys Documentations
About Verilog design:
Search through www.sunburst-design.com/papers/ for interesting articles, like:
Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock Designs
Nonblocking Assignments With Delays, Myths & Mysteries
Asynchronous & Synchronous Reset Design Techniques - Part Deux
search also: www.deepchip.com/downloadpage.html
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