Issues with writing a cyclic code encoder and decoder

[venky yadav]

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-- Company:
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-- Create Date: 15:27:16 10/07/2010
-- Design Name:
-- Module Name: enc2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
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-- Dependencies:
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-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity enc2 is

port(a : in std_logic;
clk: in std_logic;
b: out std_logic_vector(6 downto 0));

end enc2;

architecture Behavioral of enc2 is

signal temp:std_logic_vector(2 downto 0):="000";
signal p:std_logic_vector(2 downto 0):="000";
signal s:std_logic_vector(3 downto 0);
signal count:integer := 0;
begin
process(clk,a)
begin
if(clk'event and clk='1') then
b(count)<=a;
count <= count + 1;
p(2)<=a xor temp(0);
p(1)<=(a xor temp(0)) xor temp(2);
p(0)<=temp(1);
temp<=p;
b(6 downto 4)<=temp;
end if;
end process;



end Behavioral;


I am having a problem in getting the parity bits in the b(which is the output of encoder)
i am using systematic type of generation for cyclic codes so the input directly goes into the k last bits of the output i.e. b.

Thanks in advance

 

[TrickyDicky]

Re: cyclic (7,4) encoder

first. you need to reset your counter somehow. At the moment, After 7 clocks it is going to overflow the bounds of b.
p and temp are some kinds of shift register, so you are actually putting historical data into "b". Is this what you wanted to do? Im guessing the parity is incorrect because the gnereated parity is probably 2 clocks cycles too old when it is output.

 

[venky yadav]

Re: cyclic (7,4) encoder

first. you need to reset your counter somehow. At the moment, After 7 clocks it is going to overflow the bounds of b.
p and temp are some kinds of shift register, so you are actually putting historical data into "b". Is this what you wanted to do? Im guessing the parity is incorrect because the gnereated parity is probably 2 clocks cycles too old when it is output.

Actually what i was trying to do is encode the input date i.e cyclic encoding where output b contains the input in last k placs( k is length input) and the n-k places contain the parity bits...which i generated by dividing the input by generator polynomial using a shift register

I had written another type of code using for loop wherein i wanted to do this is one cycle ...which would really help me configure with ADC in FPGA spartan 3 kit.This is given as followsthis also didnt work)
entity enc1 is
port(a : in std_logic_vector(3 downto 0);
clk: in std_logic;
b: out std_logic_vector(6 downto 0));
end enc1;

architecture Behavioral of enc1 is
signal temp,p:std_logic_vector(2 downto 0):="000";
signal s:std_logic_vector(3 downto 0);
begin
process(clk,a)
begin
if(clk'event and clk='1') then
for i in 0 to 3 loop
s(i)<=a(i);
p(2)<=a(i) xor temp(0);
p(1)<=p(2) xor temp(2);
p(0)<=temp(1);
temp<=p;
end loop;
b(6 downto 4)<=temp;
b(3 downto 0)<=a;
end if;
end process;

end Behavioral;

Thnks for ur prompt reply...and i will be thankful for ur future replys...

 

[TrickyDicky]

Re: cyclic (7,4) encoder

Can I assume that "k" in both instances is 4?

For the for loop version, you know that p(2) is always set to a(3) xor temp(0) right? loops are unrolled in VHDL and the last assignment to any signal wins, which in this case is a(3).
I think in your first instance you really meant to used variables for temp and "p". Variables are updated instantly, signals are only updated at the end of a process.

 

[venky yadav]

Re: cyclic (7,4) encoder

Can I assume that "k" in both instances is 4?

For the for loop version, you know that p(2) is always set to a(3) xor temp(0) right? loops are unrolled in VHDL and the last assignment to any signal wins, which in this case is a(3).
I think in your first instance you really meant to used variables for temp and "p". Variables are updated instantly, signals are only updated at the end of a process.

Hi ....first of all thanks a lot i got the problem solved.....
ya k over here is 4....and i am goin to extend for k=27
however the variable part helped me in the process..and i was able to do it in one clock cycle .....
thnks a lot again....

one more doubt ...i didnt understand first para of above.....(p(2) is right as u told) i was not able to get "loops are unrolled in VHDL and the last assignment to any signal wins, which in this case is a(3)"

 

[venky yadav]

Re: cyclic (7,4) encoder

This is in extension with the above program.
Actually if u have idea of fire code which is binary cyclic code....so i have extended the above (7,4) cyclic code for (35,27) Fire code - a 3 burst error correcting capability code...
So the problem is in the below DECODER which uses "error trapping decoding" concept.
Code:
entity dec1 is
port(b1:in std_logic_vector(34 downto 0);clk:in std_logic;
dut std_logic_vector(26 downto 0));
end dec1;

architecture Behavioral of dec1 is

begin
process(clk,b1)
variable br:std_logic_vector(34 downto 0);
variable temp1,s:std_logic_vector(7 downto 0):="00000000";
begin
if(clk'event and clk='1') then
for i in 0 to 34 loop
s(7):=b1(i) xor temp1(0);
s(6):=s(7) xor temp1(7);
s(5):=temp1(6);
s(4):=temp1(5) xor s(7);
s(3):=temp1(4);
s(2):=s(7) xor temp1(3);
s(1):=s(7) xor temp1(2);
s(0):=temp1(1);
temp1 := s;
br(i):=b1(i);
end loop;

for j in 0 to 34 loop

s(7):= temp1(0);
s(6):=s(7) xor temp1(7);
s(5):=temp1(6);
s(4):=temp1(5) xor s(7);
s(3):=temp1(4);
s(2):=s(7) xor temp1(3);
s(1):=s(7) xor temp1(2);
s(0):=temp1(1);
temp1 := s;

if(j>=0 and j<=4 ) then
if((s(7) or s(6) or s(5) or s(4) or s(3))='0') then
d<=br(26 downto 0);
exit;
end if;
end if;

if(j>=5 and j<=7 ) then
if((s(7) or s(6) or s(5) or s(4) or s(3))='0') then
if(j=5) then
br(0):=(br(0)) xor s(2);
d<=br(26 downto 0);
exit;
elsif(j=6) then
br(0):=(br(0)) xor s(1);
br(1):=(br(1)) xor s(2);
d<=br(26 downto 0);
exit;
elsif(j=7) then
br(0):=(br(0)) xor s(0);
br(1):=(br(1)) xor s(1);
br(2):=(br(2)) xor s(2);
d<=br(26 downto 0);
exit;
end if;
end if;
end if;

if(j>=8 and j<=28 ) then
d(j-8 )<=br(j-8 );
if((s(7) or s(6) or s(5) or s(4) or s(3))='0') then
d(j-7)<=br(j-7) xor s(0);
d(j-6)<=br(j-6) xor s(1);
d(j-5)<=br(j-5) xor s(2);
d(26 downto j-4)<=br(26 downto j-4);
exit;
end if;
end if;

if(j=29) then
d(21)<=br(21);
if((s(7) or s(6) or s(5) or s(4) or s(3))='0') then
d(22)<=br(22) xor s(0);
d(23)<=br(23) xor s(1);
d(24)<=br(24) xor s(2);
d(25)<=br(25);
d(26)<=br(26);
exit;
end if;
end if;

if(j=30) then
d(22)<=br(22);
if((s(7) or s(6) or s(5) or s(4) or s(3))='0') then
d(23)<=br(23) xor s(0);
d(24)<=br(24) xor s(1);
d(25)<=br(25) xor s(2);
d(26)<=br(26);
exit;
end if;
end if;

if(j=31) then
d(23)<=br(23);
if((s(7) or s(6) or s(5) or s(4) or s(3))='0') then
d(24)<=br(24) xor s(0);
d(25)<=br(25) xor s(1);
d(26)<=br(26) xor s(2);
exit;
end if;
end if;

if(j=32) then
d(24)<=br(24);
if((s(7) or s(6) or s(5) or s(4) or s(3))='0') then
d(25)<=br(25) xor s(0);
d(26)<=br(26) xor s(1);
exit;
end if;
end if;

if(j=33) then
d(25)<=br(25);
if((s(7) or s(6) or s(5) or s(4) or s(3))='0') then
d(26)<=br(26) xor s(0);
exit;
end if;
end if;

if(j=34) then
d(26)<=br(26);
end if;

end loop;
end if;
end process;
end Behavioral;

"Now the problem is ...if I give a particular signal as input it will give the output(27 bits) same as input(the right most 27bits of 35bits) but when I want to give error in input which should give the corrected output, it is giving the signal with error itself."

 

[permute]

Re: cyclic (7,4) encoder

for i in 0 to 34 loop
s(7):=b1(i) xor temp1(0);
s(6):=s(7) xor temp1(7);
s(5):=temp1(6);
s(4):=temp1(5) xor s(7);
s(3):=temp1(4);
s(2):=s(7) xor temp1(3);
s(1):=s(7) xor temp1(2);
s(0):=temp1(1);
temp1 := s;
br(i):=b1(i);
end loop;

Are you sure this block of code does what you think it does?

Is there some reason the encoder has a serial input, but the decoder has a parallel input?

also, are you sure your encoder works? It seemed to be dividing m(x) by g(x), instead of m(x)*x^p by g(x)

 

[venky yadav]

Re: cyclic (7,4) encoder

for i in 0 to 34 loop
s(7):=b1(i) xor temp1(0);
s(6):=s(7) xor temp1(7);
s(5):=temp1(6);
s(4):=temp1(5) xor s(7);
s(3):=temp1(4);
s(2):=s(7) xor temp1(3);
s(1):=s(7) xor temp1(2);
s(0):=temp1(1);
temp1 := s;
br(i):=b1(i);
end loop;

Are you sure this block of code does what you think it does?

Is there some reason the encoder has a serial input, but the decoder has a parallel input?

also, are you sure your encoder works? It seemed to be dividing m(x) by g(x), instead of m(x)*x^p by g(x)

The encoder used is the one in the third post and extend for fire code with "g(x)=(1+x^5)*(1+x+x^3)=1+x+x^3+x^5+x^6+x^8" and the encoder used with "for loop" did work for (7,4) code ....i was not able to check for (35,27) code.
Encoder: Shifting from right end gives the m(x)*x^p by g(x) which i did so as given in Lin & Castello (Error Control Coding)

Decoder: The first loop computed my syndrome.
The second loop is used for trapping of error in the syndrome register which i checked by condition (s(7) to s(3) as zeros and hence able to correct a burst of 3 bits i.e s(2) to s(0) indicates error).
so syndrome register is shifted with the g(x) polynomial feedback activated in the second loop.
This is what I did from the concepts given in Lin & Castello.