venky yadav
Newbie level 4
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-- Company:
-- Engineer:
--
-- Create Date: 15:27:16 10/07/2010
-- Design Name:
-- Module Name: enc2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity enc2 is
port(a : in std_logic;
clk: in std_logic;
b: out std_logic_vector(6 downto 0));
end enc2;
architecture Behavioral of enc2 is
signal temp:std_logic_vector(2 downto 0):="000";
signal p:std_logic_vector(2 downto 0):="000";
signal s:std_logic_vector(3 downto 0);
signal count:integer := 0;
begin
process(clk,a)
begin
if(clk'event and clk='1') then
b(count)<=a;
count <= count + 1;
p(2)<=a xor temp(0);
p(1)<=(a xor temp(0)) xor temp(2);
p(0)<=temp(1);
temp<=p;
b(6 downto 4)<=temp;
end if;
end process;
end Behavioral;
I am having a problem in getting the parity bits in the b(which is the output of encoder)
i am using systematic type of generation for cyclic codes so the input directly goes into the k last bits of the output i.e. b.
Thanks in advance
-- Company:
-- Engineer:
--
-- Create Date: 15:27:16 10/07/2010
-- Design Name:
-- Module Name: enc2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity enc2 is
port(a : in std_logic;
clk: in std_logic;
b: out std_logic_vector(6 downto 0));
end enc2;
architecture Behavioral of enc2 is
signal temp:std_logic_vector(2 downto 0):="000";
signal p:std_logic_vector(2 downto 0):="000";
signal s:std_logic_vector(3 downto 0);
signal count:integer := 0;
begin
process(clk,a)
begin
if(clk'event and clk='1') then
b(count)<=a;
count <= count + 1;
p(2)<=a xor temp(0);
p(1)<=(a xor temp(0)) xor temp(2);
p(0)<=temp(1);
temp<=p;
b(6 downto 4)<=temp;
end if;
end process;
end Behavioral;
I am having a problem in getting the parity bits in the b(which is the output of encoder)
i am using systematic type of generation for cyclic codes so the input directly goes into the k last bits of the output i.e. b.
Thanks in advance