sabnam.koley
Newbie level 1
I am a fresher post-graduate. I have appeared for the last semester examination on June'13 for my M.Tech VLSI degree. I am very much interested in Layout domain. My M.Tech thesis paper is on "Study of Matching Layout Techniques for Analog VLSI Design" using Tanner EDA Tool. If there is any opening for a Internship in this domain, please let me know.