elektrom
Full Member level 2
Is it possible to synthesize the post-place & route netlist? Any way to do that? Is it secure to send vhdl/verilog timing model to customer for evaluation propose?
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elektrom said:Is it possible to synthesize the post-place & route netlist? Any way to do that? Is it secure to send vhdl/verilog timing model to customer for evaluation propose?
elektrom said:Is it possible to synthesize the post-place & route netlist? Any way to do that?
I think it is FPGA flow!sarath51 said:Is this regarding FPGA or ASIC Flow ? and how it is usefull