Internal bidirectional BUS in FPGA

[mmmmec]

Hi,
I am planning to implement a router mesh network inside the FPGA with bidirectional buses. Unfortunately , it seems that tristating logic is not available for internal signals.


Could anyone kindly suggest any ideas by which an internal bidirectional bus can be implemented ?

I read somewhere about the compiler automatically converting the logic to MUX based . Could any one explain it in a more better way or point to some resources ?

Thanks and Regards
[/b]

 

[sameh_yassin99]

Hello there,

Why don't you use the type "inout" for ports that you aim to use as bidirectional. I can't understand your problem exactly.

Best Wishes;

 

[mmmmec]

WARNING:Xst:2042 - Unit bidir: 8 internal tristates are replaced by logic (pull-up yes): bidir<0>, bidir<1>, bidir<2>, bidir<3>, bidir<4>, bidir<5>, bidir<6>, bidir<7>.
INFO:Xst:2261 - The FF/Latch <t2/b_0> in Unit <Top> is equivalent to the following FF/Latch, which will be removed : <t1/b_0>
INFO:Xst:2261 - The FF/Latch <t2/b_1> in Unit <Top> is equivalent to the following FF/Latch, which will be removed : <t1/b_1>
INFO:Xst:2261 - The FF/Latch <t2/b_2> in Unit <Top> is equivalent to the following FF/Latch, which will be removed : <t1/b_2>
INFO:Xst:2261 - The FF/Latch <t2/b_3> in Unit <Top> is equivalent to the following FF/Latch, which will be removed : <t1/b_3>
INFO:Xst:2261 - The FF/Latch <t2/b_4> in Unit <Top> is equivalent to the following FF/Latch, which will be removed : <t1/b_4>
INFO:Xst:2261 - The FF/Latch <t2/b_5> in Unit <Top> is equivalent to the following FF/Latch, which will be removed : <t1/b_5>
INFO:Xst:2261 - The FF/Latch <t2/b_6> in Unit <Top> is equivalent to the following FF/Latch, which will be removed : <t1/b_6>
INFO:Xst:2261 - The FF/Latch <t2/b_7> in Unit <Top> is equivalent to the following FF/Latch, which will be removed : <t1/b_7>
INFO:Xst:2261 - The FF/Latch <t2/outp_0> in Unit <Top> is equivalent to the following FF/Latch, which will be removed : <t1/outp_0>
INFO:Xst:2261 - The FF/Latch <t2/outp_1> in Unit <Top> is equivalent to the following FF/Latch, which will be removed : <t1/outp_1>
INFO:Xst:2261 - The FF/Latch <t2/outp_2> in Unit <Top> is equivalent to the following FF/Latch, which will be removed : <t1/outp_2>
INFO:Xst:2261 - The FF/Latch <t2/outp_3> in Unit <Top> is equivalent to the following FF/Latch, which will be removed : <t1/outp_3>
INFO:Xst:2261 - The FF/Latch <t2/outp_4> in Unit <Top> is equivalent to the following FF/Latch, which will be removed : <t1/outp_4>
INFO:Xst:2261 - The FF/Latch <t2/outp_5> in Unit <Top> is equivalent to the following FF/Latch, which will be removed : <t1/outp_5>
INFO:Xst:2261 - The FF/Latch <t2/outp_6> in Unit <Top> is equivalent to the following FF/Latch, which will be removed : <t1/outp_6>
INFO:Xst:2261 - The FF/Latch <t2/outp_7> in Unit <Top> is equivalent to the following FF/Latch, which will be removed : <t1/outp_7>





Hi,,

I synthesised my implementation of a bidirectional bus after unselectingthe
ADD IO BUFFERS option in the synthesis menu of the Xilinx IST . My device is Virtex 4 and I got the above message. What exactly does this mean ? and how may the pull up data affect my bidirectional data bus ?

The following is the code of my bidirectional receiver ...




ENTITY bidir IS
PORT(
bidir : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);
oe, clk : IN STD_LOGIC;
inp : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
outp : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END bidir;

ARCHITECTURE Behave OF bidir IS
SIGNAL a : STD_LOGIC_VECTOR (7 DOWNTO 0); -- DFF that stores
-- value from input.
SIGNAL b : STD_LOGIC_VECTOR (7 DOWNTO 0); -- DFF that stores
BEGIN -- feedback value.

bidir <=a when oe = '1' else (others => 'Z');
PROCESS(clk)
BEGIN
IF clk = '1' AND clk'EVENT THEN -- Creates the flipflops
a <= inp;
b <= bidir;
outp <= b;
END IF;
END PROCESS;

End behave;

 

[FvM]

I read somewhere about the compiler automatically converting the logic to MUX based. Could any one explain it in a more better way.

What's unclear with this simple fact? FPGA internal signal routing is restricted to unidirectional connections with a single driver
by design.

It's also correct, that "virtual" internal tristate drivers can be used in the design entry, if it's appropriate for your design. The
design compiler can change it to muxes, and as far as I understood, it already did in your test. You have to keep HDL rules, that
don't allow multiple drivers for a net, so you must implement a design wide set of mutual exclusive output enable signals for the
tristate-drivers.

Ideally, the design would require the same resources as when designed with multiplexers from the start. But your design also
involves registers between the signal sources and the "bus". Depending on the intended function, the place of registers and
multiplexers can be possibly changed and you may want to control all design details manually. In this case, a dedicated mux
based design is the clearer way.

 

[dmk]

I tried it, and I didn't recieve any error. And even the implementation passed without any error or warning.

Added after 1 minutes:

entity eda is
Port ( bidir : inout STD_LOGIC_VECTOR (7 downto 0);
oe, clk : in STD_LOGIC;
inp : in STD_LOGIC_VECTOR (7 downto 0);
outp : out STD_LOGIC_VECTOR (7 downto 0));
end eda;
architecture Behavioral of eda is
SIGNAL a : STD_LOGIC_VECTOR (7 DOWNTO 0); -- DFF that stores input value
SIGNAL b : STD_LOGIC_VECTOR (7 DOWNTO 0); -- DFF that stores feedback value
begin
bidir <=a when oe = '1' else (others => 'Z');
PROCESS(clk)
BEGIN
IF rising_edge(clk) THEN -- Creates the flipflops
a <= inp;
b <= bidir;
outp <= b;
END IF;
END PROCESS;
end Behavioral;

 

[FvM]

You connected the entity with it's port signals as a top entity, which creates a real bidirectional driver. The original poster apparently
intentended to connect multiple driver components to an internal bus.

 

[juan_manuell]

Instead of made a entity and use IOUT, you could define the BUS with BUFFER type. This will use a tri-state bidir internal buffer

regards

 

[nsingh95]

Hello there,

Why don't you use the type "inout" for ports that you aim to use as bidirectional. I can't understand your problem exactly.

Best Wishes;

Hi,
Please go to the gollowing site : www.atera.com/literature
You didn't specify which FPGA you are using.