Interfacing SRAM beginner question

[grubby23]

Hi,

I would like to interface my FPGA design with a SRAM chip. I looked at a related .ucf file which uses this SRAM chip and there it said:

NET sram_clk IOSTANDARD = LVCMOS33;
NET sram_clk DRIVE=16;
NET sram_clk SLEW=FAST;
...
NET sram_addr(*) IOSTANDARD = LVDCI_33;
NET sram_addr(*) DRIVE=8;
NET sram_addr(*) FAST;

Normally, I simply used the constraint file for port mapping, so could somebody please quickly explain me what is the slew and drive here? Why do I use one drive=16 and the other time drive = 8? Furthermore, where do I find out what is the IOSTANDARD, is this to be found in the SRAM documentation?

Many thanks for your input

 

[permute]

Well, in this case some of these will be ignored. I suggest looking at the SelectIO user guide for more info about the different IO standards.

In this case, LVCMOS pins can be defined as having different slew rates and drive strengths. DRIVE=16, SLEW=FAST is a setting that produces fast rise/fall times. This reduces the total propogation delay -- the amount of time between when clk changes (crosses threshold) at the input to the buffer to the time clk changes (crosses threshold) at the pin on the SRAM.

The other case really doesn't matter as DRIVE=8 isn't applicable to LVDCI. LVDCI includes some series resistance on the output drivers. The intention is to both damp out any LC oscillations, as well as terminate the line from any signals reflecting from the load back to the source. DRIVE=8 with LVCMOS is another signal integrity trick. The highest frequency content of a 2-level signal is based on the rise/fall time. A lower drive should reduce the rise/fall times and reduce EMI and ringing.

IOSTANDARD is often used when voltages other than the default are used in the design. eg, 3.3V IO vs 2.5V IO.