Inter-Stage match of Linear PA!

[fxxjssc]

pa interstage match

Dear all
My PA is two stage Class AB power amplifier, which
target ClassAB output 15dBm with 1.8V power supply @900MHz。
The structure is as following:
power stage：
structure：cascode ClassAB
input power：5dBm
power gain：10dB
output power：15dBm
input voltage swing needed：1V
bias voltage：1V
bias resistor：10Kohm
input impedance：6.5Kohm res parall with 166fF cap

drive stage：
structure：cascode ClassA
input power：-10dBm
input voltage swing：0.2V
power gain：16dB
output power：6dBm
bias voltage：1V
bias res：10Kohm
output impedance：4Kohm res parall with 373fF cap
what unsure are ：
1. is the power and gain reasonable？
2. About interstage matching, is it possible to change bias res of
power stage to control its input impedance ？
3. To match output impedance of drive stage, is it good way to tune out
the two parall cap 373fF + 166fF? for 900MHz, more than 10nH L is
is needed to tune them out and is impossible for 0.18um process.


Best wishes

 

[buckaroo]

i also wanner know how to design the interstage matching, if we only use a big cap to couple, then we can only simulate the power gain together, am i right? second, will the PA oscillate if there is no interstage matching? i am working on a 2.4GHz cmos power amplifer these days, it oscillates at the output node of the 1st stage, the architecture is the same as fxxjssc's. i need help, give me a hand please, thanks alot^^