Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Input capacitance of a MOS in digital circuits

Status
Not open for further replies.

suhasrk

Newbie level 1
Joined
Sep 11, 2009
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,287
I wanted how to know how to determine the input capacitance of an inverter. We have many parasitic capacitances like Cgd Cgs etc. Is the ip cap dependent on this. If yes how? N how Miller's theorem has to be applied?

I got to know that ip cap is just the gate cap calculated from C=εA/d formula. No parasitics and Miller's theorem is used for digital circuits as compared with analog. Is this correct? Why is this so?
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top