IC I/O Input Resistor Calculations

[Rocketman46]

Hello All,

I am a software engineer trying to do a parts stress analysis on each of the components on a design I am working on, and I am struggling with a bit of analog electronics.

I have an FPGA (3V3 I/O logic levels) connected to an ADC (connected to a 3V3 supply).

In series between the FPGA and ADC on the SCLK, CS, DIN and DOUT pins are 22.1R resistors.

How would I calculate the power dissipation, and or voltage drop across these 22.1R resistors?

Do I use the maximum I/O current and work backwards using V = I.R and then P = V.I?

Look forward to your reply,

Cheers,

Rocketman46

 

[KlausST]

Hi,

I guess there are thousands of simple tutorials, online calculators, even videos on how to calculate the power dissipation of a resistor.
--> please do a search on your own.

Also there are free and easy to use circuit simulators. They all should be able to calculate power dissipation.
*****

Generally power dissipation P = V * I.
This is rather basic. It is true for all passive devices that can´t store or convert energy. True for R, D, LEDs, transitors and so on.
(Not true for C, L, batteries, motors...)

V is always measured across the device (along the current flow)

This means: if you have a resistor, one leg at 3.3V and the other at 3.1V --> then you have to use the voltage across them which is (3.3V - 3.1V) = 0.2V

And according Ohm´s law (also very basic) the current through the resistor: I = V / R (again here the voltage across the resistor)
I expect you to be able to rearrange Ohm´s law to get V and R respectiviely.

****

In your case:
It´s not important "how much current the output can drive" but it´s important "how much the input will draw".

****
Until now ... all basic.

So it´s time to step into some "more complicated details":

The current is not continuous!
* There may be time when the current is flowing (depending on pin function, pin input characteristics)
* and the pin (and trace) acts as a capacitance. Thus you get additional "capacitive current". Here resistor P = 0.5 * V * V * C for each signal edge.


*****
In most cases the power dissipation can be ignored.

Klaus

 

[dick_freebird]

I imagine that those values may have been chosen just
to "roughly match the line" (a fraction of Z=50, the rest
being internal to the part's output driver). If the other end
is a plain CMOS input you'll never see enough power to
hurt anything. On an output line, you "could" but only in
a heavy continuous load kind of fault condition (even 5V
and 22 ohms into short, is only 25mA and that's pretty
survivable if it's (say) a "5mA" output qualified to 85C at
that load.

If you exclude hard faults I don't think those resistors
mean anything. Of course you still have to do the work
and write the memo.

 

[KlausST]

(even 5V
and 22 ohms into short, is only 25mA

I expect 250mA. Typo?
Klaus

 

[D.A.(Tony)Stewart]

I have an FPGA (3V3 I/O logic levels) connected to an ADC (connected to a 3V3 supply).

In series between the FPGA and ADC on the SCLK, CS, DIN and DOUT pins are 22.1R resistors.

How would I calculate the power dissipation, and or voltage drop across these 22.1R resistors?

3V3 logic have typically < 25 ohm drivers +/- wide tolerance. Adding 22R1 to the source reduces mismatch of impedance on very fast risetimes to "50 ohm " traces going into high impedance CMOS with a few pF load. This reduces overshoot and eliminates ringing.

So they only conduct only a small current (3.3V / (25+22) = 21 mA for about a nanosecond at the transition rate, so not much energy, negl. heat rise.

It could add up to 40 50 or 60 and is better to be lower than 50 as Rs increases with junction temperature ( + ambient stress)

Bottom line: Ignore effects on MTBF.

FWIW
Most logic IC's rated for 3.6V max that run at 3.3V use similar drivers that look like this below ; They normally rate worst case at ~ Vcc = 3V instead of 3.3V for Vol which implies Rs driver resistance.

If you want to stress the board operate it at +/- 10% voltage with heat and dry ice and check for FPGA timing errors. (race conditions with your self-test program

 

[KlausST]

(3.3V / (25+22) = 21 mA

Again (post#4) Why?
My math says 70mA.

*****

Adding 22R1 to the source reduces mismatch of impedance

for this, the resistors need to be at the driver side of the trace.
Now the question is: is the FPGA considered as driver, or the ADC?
On SPI interfaced ADC I´d consider the FPGA as driver, but still I´v seen the Rs at the ADC side.

*****

Without seeing the schematic and PCB layout ... we can only guess. Guess about interface and function of the Rs.
@OP: Please provide schematic and PCB layout.

Klaus

 

[D.A.(Tony)Stewart]

TY @KlausST
I must not get distracted while watching a movie with my lack of attention to simple things like refocusing the distance from my side Windoze monitor to my trifocals
3 / 3 / 47 = 21 oops.

74ALCVxx 3.6V logic has a rise time of 1ns. current depends on lumped trace capacitance of 50 ohms (~3cm/pF) + Cin (3.5 pF) + Rg
(Tr=1ns) T-line effects < 10 cm may be ignored, aka Bergeron method,

Load C cannot be ignored for risetime effects.