initialise the counter with desired value verilog/vhdl

[mosfets.bjt]

i want to design a counter in verilog or vhdl that should start from the desired value, can anyone help?

 

[user_asic]

If your synthesizer allows you to initialize a reg on power on, then you can do that. Best practice is to have a "reset" state where all regs, including your counter, are initialized to desired values.

 

[mosfets.bjt]

my synthesizer's name is quartus, for altera
can u \write any eaxmple like what if i want to initialise a 3 bit counter at the value of 3 instead of zero??

Added after 22 minutes:

ok i have found the way
thanks

 

[dilinx]

reset is the best option bcoz it suits all situations......