FlyingDutch
Advanced Member level 1
- Joined
- Dec 16, 2017
- Messages
- 458
- Helped
- 45
- Reputation
- 92
- Reaction score
- 55
- Trophy points
- 28
- Location
- Bydgoszcz - Poland
- Activity points
- 5,020
Hello,
I am wondering if there is any form of inheritance in VHDL or Verilog. I am not very expierienced user of these languages, but several times in my projects (VHDL mostly) I noticed that inheritance would simplify them. I mean inheritance as it is defined in object oriented languages like Java or C++. The ability to extend existing in project entities/modules can save many time during development.
If such option exists, for what languages and tools for synthesis (FPGA).
Regards
I am wondering if there is any form of inheritance in VHDL or Verilog. I am not very expierienced user of these languages, but several times in my projects (VHDL mostly) I noticed that inheritance would simplify them. I mean inheritance as it is defined in object oriented languages like Java or C++. The ability to extend existing in project entities/modules can save many time during development.
If such option exists, for what languages and tools for synthesis (FPGA).
Regards