Influence of VerilogA code on FFT in cadence

[Chinmaye]

Dear all,
I am trying to simulate a 12-bit pipeline ADC in cadence. In the first 4 stages of the ADC are MDAC and comparators designed using PMOS and NMOS. The LSB stages are coded using Verilog A model. Now, I give a sine wave of the input and try to take a fft of it. I wanted to know how verilogA affects the fft plot?

 

[jjx]

Cannot be answered per se, so anything between a lot and nothing would be the most correct answer. It all depends on how accurate you do your models.