nick123
Member level 2
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 entity MY_PROG is port( Real : in std_logic_vector (31 downto 0); Imag : in std_logic_vector (31 downto 0); Realo : out std_logic_vector (31 downto 0); Imago : out std_logic_vector (31 downto 0); clk, Request: in std_logic; ); end MY_PROG ;
Is this valid to use "real" as a input port list in the entity as its predefined in vhdl.
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