Implementing a large register file

[asicman]

Hello,

I am trying to find the best way to implement a very large register file (1030+ 16-bit registers). On the write side I am using s straight forward approach:

process(CLK)
if rising_edge(CLK) then
  if (RST = '1') then
     ...<RESET CODE>
  else
    if (ADDR = C_ADDR_REG0) then
      reg_file.REG0 <= WR_DATA;
    end if
    if (ADDR = C_ADDR_REG1) then
      reg_file.REG1 <= WR_DATA;
    end if
    <.....>

my concern is with the read side, I was planning on using a MUX approach

with ADDR select
  RD_DATA <= reg_file.REG0 when C_ADDR_REG0 ,
  <...>

but I am afraid that with the amount of registers we are dealing with, the MUX resources would be huge and the design would not be able to meet timing or route constraints...does anybody else have a better approach I could use?

 

[FvM]

Today's FPGA have internal RAM for similar purposes. The vendor tools are typically able to extract the RAM component instantiation from your VHDL code, if the implemented behaviour fits the hardware requirements. The tools documentation tells in detail how to, e.g. the A.ltera Q.uartus software handbook. They also have simple code templates to demonstrate the method.

The other method is explicite instantiation of RAM components from vendor specific libraries. This assures, that the register file operation meets all requirements of the real hardware, e.g. regarding timing of addresses, data and control signals.

 

[Maxwell077]

In Xilinx FPGAs, you may also use IPCoreGenerator to implement a memory elements such as BlockRAMs. By using language templates, they explain you how to create a RAM, ROM etc. This ways are easiest to write or read a value from RAM&ROM.

 

[asicman]

This can't be done with a RAM block since, the values written into the register need to be used by other blocks (i.e. multiple registers need to be read by multiple blocks at the same time), a RAM with a single or even a dual output for data would not cut it.