Implementation of cyclic redundancy check (crc4) using vhdl on fpga

[hm1622]

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity crc1 is
port(data_in:in std_logic_vector(3 downto 0);
poly:in std_logic_vector(4 downto 0):="10011";
crcut std_logic_vector(3 downto 0));
end crc1;

architecture Behavioral of crc1 is
signal data_in1:std_logic_vector(7 downto 0):="00000000";
begin
process(data_in1)
variable r1:std_logic_vector(4 downto 0):="00000";
begin
data_in1 <= data_in & "0000";
if(data_in1(7)='0') then
r1:=data_in1(7 downto 3) xor "00000";
else
r1:=data_in1(7 downto 3) xor poly;
end if;

for i in 2 downto 0 loop
r1:=r1(3 downto 0) & data_in1(i);
if(r1(4)='0') then
r1:= r1 xor "00000";
else
r1:= r1(4 downto 0) xor poly;
end if;
end loop;
crc<= r1(3 downto 0);

end process;

end Behavioral;




can anyone please help me in to understand this VHDL code for crc4.the input node "poly4" is ignored..i am not understand why it is ignored.
if any one have idea about VHDL code please help me hint to understand this codes step by step.

 

[qieda]

Hi,

I would do

data_in1 <= data_in & "0000";

this outside the process

and make your process sensitive to all inputs

e.g.

....
architecture Behavioral of crc1 is
signal data_in1:std_logic_vector(7 downto 0):="00000000";
begin

data_in1 <= data_in & "0000";

process(data_in1, poly)
variable r1:std_logic_vector(4 downto 0):="00000";
begin
if(data_in1(7)='0') then
r1:=data_in1(7 downto 3) xor "00000";
else
r1:=data_in1(7 downto 3) xor poly;
end if;
....

regards

 

[hm1622]

can you please explain me in detail.i have change the code as you have mention but still "poly4" is ignored by altera max plus 2.can you write the whole program.

 

[qieda]

Just to make it clear for me.

What do you mean with poly4 is ignored.
My understanding was, that bit4 of the poly input is not used. Is this correct?

regards

 

[FvM]

By this code line, the MSB of r1 respectively poly(4) is unconditionally discarded:

r1:=r1(3 downto 0) & data_in1(i);

As far as I understand, the leading '1' of a CRC poly is actually a dummy bit (known to be '1') and may be possibly ignored by a CRC code.

 

[hm1622]

yes for that i am asking to you.why the poly4 is ignored??it is necessary bit as input.because we cant generate crc with out polynomial bits.cay you please solve the above code.

---------- Post added at 15:33 ---------- Previous post was at 15:28 ----------

By this code line, the MSB of r1 respectively poly(4) is unconditionally discarded:

r1:=r1(3 downto 0) & data_in1(i);

As far as I understand, the leading '1' of a CRC poly is actually a dummy bit (known to be '1') and may be possibly ignored by a CRC code.

may be but i have not detail idea about crc.so are you sure that in crc the first MSB bit is dummy bit and its value is '1'?

 

[qieda]

for i in 2 downto 0 loop
r1:=r1(3 downto 0) & data_in1(i);

-- data_in1(2 downto 0) is 0 this will set everything to 0 and you do it 3 times in a loop
-- since I'm doing verilog, I do not know how VHDL calculates r1(4) in this case
-- maybe it sets the r1(4) also to 0
-- then the output is always 0

did you do simulations?
for CRC I think you can find lot of code in the internet


regards

 

[FvM]

I confess, I wasn't motivated to check the code against a known CRC algorithm, but in fact all CRC polynomials have a leading '1' that's not used in the calculation. You'll realize this by comparing with other implementations, see e.g. Cyclic redundancy check - Wikipedia, the free encyclopedia. Your code is apparently implementing CRC-4-ITU.