roofingboom
Member level 4
I Need to implement a low pass filter in an FPGA. I am very confident with FPGA's and DSP theory. I am not confident in selecting a DSP filter.
My A/D's are sampling at 1MHz. I want my low pass to be at 100Hz. The problem i am noticing is that 1e2/1e6 is a small number and the actual quantized model doesn't follow the passband of actual model. My specs for the filter are very arbitrary. I have a 15khz signal that i want to extract the DC component out of. So the gain should be 1 and roll off at 100Hz is fine enough to detect DC component. I would like some insight into what i should do? Should i down sample then implement the filter because the fc/fs ratio will be bigger?
Plus should i be using a FIR or IIR what type etc? I know about all the basic filters but i just don't know what is better for certain apps in implementation.
My A/D's are sampling at 1MHz. I want my low pass to be at 100Hz. The problem i am noticing is that 1e2/1e6 is a small number and the actual quantized model doesn't follow the passband of actual model. My specs for the filter are very arbitrary. I have a 15khz signal that i want to extract the DC component out of. So the gain should be 1 and roll off at 100Hz is fine enough to detect DC component. I would like some insight into what i should do? Should i down sample then implement the filter because the fc/fs ratio will be bigger?
Plus should i be using a FIR or IIR what type etc? I know about all the basic filters but i just don't know what is better for certain apps in implementation.
