implement FPGA circuit written in vhdl

[dpt30]

Hello

I wrote a code in vhdl for a divisor of positive integers (eg 80:7 = 11, remainder = 3). my problem lies in the implementation of this code on FPGA spartan xc3s200 (freq = 50 MHz) to display the result on the 8 LEDs of the FPGA card.
My divider circuit consists of a dividend (7 bits) and a divisor (4 bits), the code will output a quotient (4 bits) and a residue ( 7 bits).
So I'm back on the buttons that control the LEDs the dividend and divisor to see the result of quotient and remainder taking into account the problems of clock generation.

Could you give me some tracks?

Thank you

 

[mrflibble]

Do you have any vhdl code? Right now people who would want to help you will have to guess a lot of details.

I assume that the divider works since of course you will have put it through simulation. Right?

Anyways, you could try first outputting a constant bit pattern to the leds and see if that works. Then input from buttons into registers and then output that to the leds. That should take care of any pin assignment surprises...

After that you can just write a case statement using the button inputs to select what register to output on your leds.

Again, your current vhdl code plus your description of what does and what doesn not work would help people in helping you...

 

[dpt30]

thank you

the behavioral model simulation with xilinx works perfectly , but when i do post place & route simulation i get in quotient and remainder 0000000 :|
i think i have a problem with the clock maybe i should use a clock divider but in which frequence ?

 

[mrflibble]

Could you give the code for the entire module?

Also, maybe just divide the clock by 1024 if the rest of the design allows it, and see if it magically works.