Illegal reference to net -problem

[eng_msa_8_8]

always @(State)
begin
F = 1'b0;
G = 1'b0;
if (State == Go1)
F = 1'b1;
else if (State == Go2)
G = 1'b1;
end




** Error: E:/A STUDY/VERILOG/VERILOG/projects/test1.v(27): (vlog-2110) Illegal reference to net "F".
** Error: E:/A STUDY/VERILOG/VERILOG/projects/test1.v(28): (vlog-2110) Illegal reference to net "G".
** Error: E:/A STUDY/VERILOG/VERILOG/projects/test1.v(30): (vlog-2110) Illegal reference to net "F".
** Error: E:/A STUDY/VERILOG/VERILOG/projects/test1.v(32): (vlog-2110) Illegal reference to net "G".



where is the problem ???????????????


here is the whole code

module test ;
parameter Idle = 2'b00,
Go1 = 2'b01,
Go2 = 2'b10;
reg [1:0] State;
wire Reset,F,G;
wire t1;
reg t2;
reg clock;
initial begin clock = 1'b1;
forever #5 clock = !clock;
end


always @(posedge clock or posedge Reset)
if (Reset)
State <= Idle;
else
case (State)
Idle:State <= Go1;
Go1 : State <= Go2;
Go2 : State <= Idle;
endcase

always @(State)
begin
F = 1'b0;
G = 1'b0;
if (State == Go1)
F = 1'b1;
else if (State == Go2)
G = 1'b1;
end

endmodule

 

[rca]

if you declare at reg instead do you have the same issue?

 

[eng_msa_8_8]

yes
either (reg) nor (wire) the same error

 

[shitansh]

Hi

Try this one

module test ;

  parameter Idle = 2'b00,
            Go1  = 2'b01,
            Go2  = 2'b10;
            
  reg  [01:00] C_State, N_State;    
  reg          Reset;
  reg          F,G;
  wire         t1;
  reg          t2;
  reg          clock;

  initial 
    begin 
      clock = 1'b1;
      forever #5  clock = !clock;
    end

  initial 
    begin 
      Reset = 1'b1;
      #25 Reset = 1'b0;
    end

// sequential logic of state machine
  always @(posedge clock or posedge Reset)
    begin
      if (Reset)
        C_State <= Idle;
      else
        C_State <= N_State;
    end

// combinational logic of state machine    
  always @ (C_State)
    begin
      case (C_State)
        Idle    : N_State = Go1;
        Go1     : N_State = Go2;
        Go2     : N_State = Idle;	
        default : N_State = Idle;      
      endcase
    end

// output logic of state machine 
  always @(posedge clock)
    begin
      case (N_State)
        Idle    : begin 
                    F <= 1'b0;
                    G <= 1'b0;
                  end 
        Go1     : begin 
                    F <= 1'b1;
                    G <= 1'b0;        
                  end 
        Go2     : begin 
                    F <= 1'b0;
                    G <= 1'b1;        
                  end 
        default : begin 
                    F <= 1'b0;
                    G <= 1'b0;        
                  end 
      endcase        
    end      
endmodule

HTH
Shitansh Vaghela

 

[eng_msa_8_8]

oh realy thanx v.much
it works

 

[karan1207]

I have a question for you shitansh.
I ma getting the error of "(vlog-2110) illegal reference to net" for a inout variable. Is it that we cannot declare a inout as a reg type?

 

[shitansh]

It depends, how you have written code for bidirectional pin. Basically a open drain pin.

 

[karan1207]

could you elaborate. I will tell you the problem I am facing.
I want to implement the right shift on a register with data- in input. So, I have to define that register as inout. When I define it as reg, the problem starts....

 

[shitansh]

send me the part of code where the problem is. I will give solution.