eng_msa_8_8
Junior Member level 3
always @(State)
begin
F = 1'b0;
G = 1'b0;
if (State == Go1)
F = 1'b1;
else if (State == Go2)
G = 1'b1;
end
** Error: E:/A STUDY/VERILOG/VERILOG/projects/test1.v(27): (vlog-2110) Illegal reference to net "F".
** Error: E:/A STUDY/VERILOG/VERILOG/projects/test1.v(28): (vlog-2110) Illegal reference to net "G".
** Error: E:/A STUDY/VERILOG/VERILOG/projects/test1.v(30): (vlog-2110) Illegal reference to net "F".
** Error: E:/A STUDY/VERILOG/VERILOG/projects/test1.v(32): (vlog-2110) Illegal reference to net "G".
where is the problem ???????????????
here is the whole code
module test ;
parameter Idle = 2'b00,
Go1 = 2'b01,
Go2 = 2'b10;
reg [1:0] State;
wire Reset,F,G;
wire t1;
reg t2;
reg clock;
initial begin clock = 1'b1;
forever #5 clock = !clock;
end
always @(posedge clock or posedge Reset)
if (Reset)
State <= Idle;
else
case (State)
Idle:State <= Go1;
Go1 : State <= Go2;
Go2 : State <= Idle;
endcase
always @(State)
begin
F = 1'b0;
G = 1'b0;
if (State == Go1)
F = 1'b1;
else if (State == Go2)
G = 1'b1;
end
endmodule
begin
F = 1'b0;
G = 1'b0;
if (State == Go1)
F = 1'b1;
else if (State == Go2)
G = 1'b1;
end
** Error: E:/A STUDY/VERILOG/VERILOG/projects/test1.v(27): (vlog-2110) Illegal reference to net "F".
** Error: E:/A STUDY/VERILOG/VERILOG/projects/test1.v(28): (vlog-2110) Illegal reference to net "G".
** Error: E:/A STUDY/VERILOG/VERILOG/projects/test1.v(30): (vlog-2110) Illegal reference to net "F".
** Error: E:/A STUDY/VERILOG/VERILOG/projects/test1.v(32): (vlog-2110) Illegal reference to net "G".
where is the problem ???????????????
here is the whole code
module test ;
parameter Idle = 2'b00,
Go1 = 2'b01,
Go2 = 2'b10;
reg [1:0] State;
wire Reset,F,G;
wire t1;
reg t2;
reg clock;
initial begin clock = 1'b1;
forever #5 clock = !clock;
end
always @(posedge clock or posedge Reset)
if (Reset)
State <= Idle;
else
case (State)
Idle:State <= Go1;
Go1 : State <= Go2;
Go2 : State <= Idle;
endcase
always @(State)
begin
F = 1'b0;
G = 1'b0;
if (State == Go1)
F = 1'b1;
else if (State == Go2)
G = 1'b1;
end
endmodule