I need a clock fanout buffer with very low additive phase noise in PLL

[fenfei]

I want to use an 10MHz OCXO to drive four PLL ref input,So there is a 1:4 clock fanout buffer needed. The OCXO phase noise is as low as -150dBc/Hz@10kHz, So the buffer must have a very low additive phase noise,could anyone give me some suggestion?
I have found some clock fanout buffer ,but there is no phase noise specification in their datasheet. Or could anyone tell me what jitter the fanout buffer should have when the phase noise is below -150dBc/Hz@10kHz?
Thanks!

 

[biff44]

74act logic will meet the frequency and phase noise. What logic are you trying to intergace it to.

 

[fenfei]

Thanks!
The PLL ref input is CMOS logic.
I think You mean that using the OCXO drive four 74act logic,then the 74act logic output drive the PKLL ref. Is that right?
But I don't sure if the OCXO could drive four 74act logic input.

 

[tony_lth]

Add buffer amplfier

 

[fenfei]

I found TI has such low jitter clock fanout buffer.