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I have problem while simulating DLL (lock o/p switching)

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tarun_taurus

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DLL lock o/p switching

hi, i am simulating a DLL and it is suppose to lock at 800MHz.
the issue is after locking it again shows un-locking(digital o/p goes zero) but the frequency of the output nodes of various delay lines remains same (800MHz with .5MHz variation)

Can someone suggest what is the issue with my lock signal ?
 

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