How to write VHDL code for 2 inputs A and B and 1 output Q(14:0)?

[voho]

Hi all,

I have 2 inputs A and B and 1 output Q(14:0);
I want to do this in vhdl:

If a=5 and B=10 then Q=000001111111111

Thank's in advance

regards
voho

 

[nand_gates]

Re: how to do in vhdl

Here is how to do it!!

library ieee;
use ieee.std_logic_1164.all;

entity my_logic is
  
  port (
    A : in  std_logic_vector(14 downto 0);
    B : in  std_logic_vector(14 downto 0);
    Q : out std_logic_vector(14 downto 0));

end my_logic;

architecture behave of my_logic is

begin  -- behave
process (A,B)
begin  -- process
if (a="000000000000101" and B = "000000000001010") then
  Q <= "000001111111111";
else
  Q <= "000000000000000";
end if;
end process;


end behave;

 

[Kukaz]

Re: how to do in vhdl

OR SO

library ieee;
use ieee.std_logic_1164.all;

entity my_logic is

port (
A : in std_logic_vector(14 downto 0);
B : in std_logic_vector(14 downto 0);
Q : out std_logic_vector(14 downto 0));

end my_logic;

architecture behave of my_logic is
begin

Q <= "000001111111111" WHEN (a="000000000000101" and B = "000000000001010") ELSE "000000000000000";

end behave;

 

[maksya]

Re: how to do in vhdl

In my opinion, your code needs to be corrected this way:

...
A : in std_logic_vector(2 downto 0);
B : in std_logic_vector(3 downto 0);

...
Q <= "000001111111111" WHEN (a="101" and B = "1010") ELSE