How to write a loop n VHDL - code not working

[shiny1]

Hi All,

I wrote a 4bit updown binary counter component which gives 0-15 and 15-0 based on my requirement. Now I wrote a Lookup table where I can use this components output as input. Also I need to change data inputs to the look up table based on the counter output . For Example if Counter output= "0000" - "1111" my datainput should be '0', for the next cycle it should be '1'. So I thought I should write a loop but I don't know how.

For simplicity I am not adding the counter code but I can assure you its working.

use ieee.numeric-std.all;
use ieee.std_logic_unsigned.all;

entity tp(datag  : inout std_logic := '0';
counteo : inout std_logic_vector (3 downto 0 );
outp : inout std_logic);
end tp;
architecture behavioral of tp is 
begin

component count is port (
----t he output is the one am including here
countero: out std_logic_vector ( 3 down to 0 ));

component Lookup is port (
inp : in std_logic_vector ( 3 downto 0 );
writeen : in std_logic;
Data : in std_logic;
Outp: inout std_logic;
RamData : in std_logic_vector (15 downto 0 ) ;
Mode_ram : in std_logic);
end component;

signal write_en : std_logic := '0';
begin

LUT : Lookup port map (countero , write_en,data,outp,"1111111110000111",'1');'

process
variable i : integer;
begin

-- I need to write a loop which allows me to change write en and data pins based on countero
i := 0;
i:= conv_integer(countero);
while (i< 15) loop
data := '0';
write_en = '0';
end loop;

i := '0';
i := conv_integr (countero);
while (i< 15 ) loop --- am assuming this goes to nxt cycle of 0-15
data := '1';
write : = '0';
end loop;


------------------------- The loop code is not working not at all!!!!!  Its not going into the loop at all...Pls Help

end process;
end behavioral;

 

[FvM]

while (i< 15) loop
data := '0';
write_en = '0';
end loop;

The loop code is either not "executed" at all or waiting forever, depending on the value of i. Furthermore it's not doing anything useful.

Apparently you're completely misunderstanding the purpose of HDL iteration statements. They are used to generate parallel code, not creating a sequence in time.

Do you have access to a VHDL text book?

 

[shiny1]

while (i< 15) loop
data := '0';
write_en = '0';
end loop;

The loop code is either not "executed" at all or waiting forever, depending on the value of i. Furthermore it's not doing anything useful.

Apparently you're completely misunderstanding the purpose of HDL iteration statements. They are used to generate parallel code, not creating a sequence in time.

Do you have access to a VHDL text book?

Ok that was a bad example all am trying to do is to set values of data and write_en based on the counter outputs. What is the best way to do that. i.e.; 0-15 a value and the next cycle a diff combination value. How can I achieve that.

 

[FvM]

For Example if Counter output= "0000" - "1111" my datainput should be '0', for the next cycle it should be '1'. So I thought I should write a loop but I don't know how.

I don't see how a loop construct should work here. Scheduling an action for the next cycles involves a clock and a kind of state machine or at least state memory.

 

[shiny1]

Sir, is there any way I could change the inputs to the Look up component based on the input If I introduce a clock.

 

[FvM]

Of course you are able to change the signals, but based on which input? Apparently the entity tp doesn't have any explicite inputs, only inout ports, and no clock at all.

The problem seems to turn out more and more as unclear question based on an incomplete code snippet.

 

[shiny1]

Even am confused as to how to design the tp or top level component, All I have is this counter which generates 0000-1111 and a Lookup which gives a different output based on the data and writeenable and the inp pin. Now I wanted ot create a top level entity which gives the counter output to Lookup input and then set data and write enable pins i;e for the first 0000-1111 cycle it should set say data= '0',write enable =1 and then nxt cycle data should be 1 and write enable should be '0' . I know the problem but I don't know how to design the top level component.

 

[TrickyDicky]

I suggest that you think about the circuit you want rather than the code. The code only describes the circuit, and if you dont know what circuit you want, you cannot write the code.

loops in VHDL unroll into parrallel logic.