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How to write a good VHDL code ?

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yifen

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good vhdl styl

Writing a VHDL code is easy, but to write a GOOD and SYNTHESIBLE VHDL code is not trivial.
Is there any guide or example for a better VHDL coding style ??
 

how to write good vhdl code

Opencores has this Coding Style:

**broken link removed**

Out there there are lots of guidelines, or coding style rules for VHDL
 

The attached guide describes statements related to synthesis.

delay (delayed by technology)
 

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