How to use Tcl/Tk with VHDL

[James_Wade]

I am new to both VHDL and Tcl/Tk. Straight to question: I want to know how to use Tcl/Tk in Modelsim. Suppose I do not know anything in Tcl/Tk, but I have the following VHDL code for a full adder to start with. What can I do with it using Tcl/Tk and what steps should I take.I am using Quartus Prime Standard Edition and Modelsim with Altera Cyclone FPGA.

---

Code C - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
LIBRARY ieee;
 USE ieee.std_logic_1164.all;
 USE ieee.std_logic_signed.all;
 ENTITY adder IS
--H&G are 8 bit inputs 
--M is 8-bit output 
 
PORT (carryin : IN STD_LOGIC;
        X,Y   : IN STD_LOGIC;
        S         : OUT STD_LOGIC;
        carryout: OUT STD_LOGIC);
 END adder;
 
 ARCHITECTURE Behaviour OF adderk IS 
--SIGNALS ARE VARIABLES THAT WE WILL SIGN OUR OUTPUT VARIABLES TO
Signal Sum : STD_LOGIC;
BEGIN 
 
    Sum <= X XOR B XOR carryin;
    carryout <= X AND B AND carryin AND (A XOR B);
    M<=Sum;
END Behaviour;

---

 

[TrickyDicky]

What are you expecting tcl to do for you? TCL stands for Tool Command Language and is used to drive modelsim or Quartus instead of using the GUI. It does not replace writing VHDL.

So, as a basic start in modelsim (and what you'll use most of the time) from the command line:

---

Code TCL - [expand]
1
2
3
4
5
6
7
8
9
#compile your VHDL
vcom adder.vhd
vcom adder_tb.vhd
 
# start simulation
vsim adder_tb
 
# run the simulation
run 1 us

---