twfly
Newbie level 4
i design a PLL,but i don not know how to use cadence to simulate the PLL output noise and jitter.have someboy know how to simulate it ?can you teach me?thanks
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Thank for your PDF document. I will research this.oermens said:http://www.cdnusers.org/community/virtuoso/resources/ctp_cdnlivesv2007_Thibieroz.pdf
Yes ,you are right.The noise of each block has been simulated by me.and i have caculated the PLL output jitter by using matlab.But i want to know how to direct simulate the PLL output noise or jitter...dinesh agarwal said:you can use PSS + PNOISE analysis, to simulate individual block phase noise.
Sorry ,i can not understand your mean. can i ask you what are the means of the vol1 and 2??oermens said:Noise Aware PLL Flow is also covered in Spectre RF documentation (User Guide, Theory vol1 and 2)